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AddressUnit: 8
Accessible over:
Group NOC.rcs__axi Mem with fixed address
| Address | EndAddress | Name | Description |
|---|---|---|---|
| 0x00000000 | ffe_coeff_set0_0 | placeholder | |
| 0x00000004 | ffe_coeff_set0_1 | placeholder | |
| 0x00000008 | ffe_coeff_set0_2 | placeholder | |
| 0x0000000c | ffe_coeff_set0_3 | placeholder | |
| 0x00000010 | ffe_coeff_set0_4 | placeholder | |
| 0x00000014 | ffe_coeff_set1_0 | placeholder | |
| 0x00000018 | ffe_coeff_set1_1 | placeholder | |
| 0x0000001c | ffe_coeff_set1_2 | placeholder | |
| 0x00000020 | ffe_coeff_set1_3 | placeholder | |
| 0x00000024 | ffe_coeff_set1_4 | placeholder | |
| 0x00000028 | ffe_coeff_set2_0 | placeholder | |
| 0x0000002c | ffe_coeff_set2_1 | placeholder | |
| 0x00000030 | ffe_coeff_set2_2 | placeholder | |
| 0x00000034 | ffe_coeff_set2_3 | placeholder | |
| 0x00000038 | ffe_coeff_set2_4 | placeholder | |
| 0x0000003c | ffe_coeff_set3_0 | placeholder | |
| 0x00000040 | ffe_coeff_set3_1 | placeholder | |
| 0x00000044 | ffe_coeff_set3_2 | placeholder | |
| 0x00000048 | ffe_coeff_set3_3 | placeholder | |
| 0x0000004c | ffe_coeff_set3_4 | placeholder | |
| 0x00000050 | ffe_coeff_set4_0 | placeholder | |
| 0x00000054 | ffe_coeff_set4_1 | placeholder | |
| 0x00000058 | ffe_coeff_set4_2 | placeholder | |
| 0x0000005c | ffe_coeff_set4_3 | placeholder | |
| 0x00000060 | ffe_coeff_set4_4 | placeholder | |
| 0x00000064 | ffe_coeff_set5_0 | placeholder | |
| 0x00000068 | ffe_coeff_set5_1 | placeholder | |
| 0x0000006c | ffe_coeff_set5_2 | placeholder | |
| 0x00000070 | ffe_coeff_set5_3 | placeholder | |
| 0x00000074 | ffe_coeff_set5_4 | placeholder | |
| 0x00000078 | ffe_coeff_set6_0 | placeholder | |
| 0x0000007c | ffe_coeff_set6_1 | placeholder | |
| 0x00000080 | ffe_coeff_set6_2 | placeholder | |
| 0x00000084 | ffe_coeff_set6_3 | placeholder | |
| 0x00000088 | ffe_coeff_set6_4 | placeholder | |
| 0x0000008c | ffe_coeff_set7_0 | placeholder | |
| 0x00000090 | ffe_coeff_set7_1 | placeholder | |
| 0x00000094 | ffe_coeff_set7_2 | placeholder | |
| 0x00000098 | ffe_coeff_set7_3 | placeholder | |
| 0x0000009c | ffe_coeff_set7_4 | placeholder | |
| 0x000000a0 | ffe_coeff_set8_0 | placeholder | |
| 0x000000a4 | ffe_coeff_set8_1 | placeholder | |
| 0x000000a8 | ffe_coeff_set8_2 | placeholder | |
| 0x000000ac | ffe_coeff_set8_3 | placeholder | |
| 0x000000b0 | ffe_coeff_set8_4 | placeholder | |
| 0x000000b4 | ffe_coeff_set9_0 | placeholder | |
| 0x000000b8 | ffe_coeff_set9_1 | placeholder | |
| 0x000000bc | ffe_coeff_set9_2 | placeholder | |
| 0x000000c0 | ffe_coeff_set9_3 | placeholder | |
| 0x000000c4 | ffe_coeff_set9_4 | placeholder | |
| 0x000000c8 | 0x000000cb | (Not allocated) | |
| 0x000000cc | ffe_coeff_set10_0 | placeholder | |
| 0x000000d0 | ffe_coeff_set10_1 | placeholder | |
| 0x000000d4 | ffe_coeff_set10_2 | placeholder | |
| 0x000000d8 | ffe_coeff_set10_3 | placeholder | |
| 0x000000dc | ffe_coeff_set10_4 | placeholder | |
| 0x000000e0 | ffe_coeff_set11_0 | placeholder | |
| 0x000000e4 | ffe_coeff_set11_1 | placeholder | |
| 0x000000e8 | ffe_coeff_set11_2 | placeholder | |
| 0x000000ec | ffe_coeff_set11_3 | placeholder | |
| 0x000000f0 | ffe_coeff_set11_4 | placeholder | |
| 0x000000f4 | ffe_coeff_set12_0 | placeholder | |
| 0x000000f8 | ffe_coeff_set12_1 | placeholder | |
| 0x000000fc | ffe_coeff_set12_2 | placeholder | |
| 0x00000100 | ffe_coeff_set12_3 | placeholder | |
| 0x00000104 | ffe_coeff_set12_4 | placeholder | |
| 0x00000108 | ffe_coeff_set13_0 | placeholder | |
| 0x0000010c | ffe_coeff_set13_1 | placeholder | |
| 0x00000110 | ffe_coeff_set13_2 | placeholder | |
| 0x00000114 | ffe_coeff_set13_3 | placeholder | |
| 0x00000118 | ffe_coeff_set13_4 | placeholder | |
| 0x0000011c | ffe_coeff_set14_0 | placeholder | |
| 0x00000120 | ffe_coeff_set14_1 | placeholder | |
| 0x00000124 | ffe_coeff_set14_2 | placeholder | |
| 0x00000128 | ffe_coeff_set14_3 | placeholder | |
| 0x0000012c | ffe_coeff_set14_4 | placeholder | |
| 0x00000130 | ffe_coeff_set15_0 | placeholder | |
| 0x00000134 | ffe_coeff_set15_1 | placeholder | |
| 0x00000138 | ffe_coeff_set15_2 | placeholder | |
| 0x0000013c | ffe_coeff_set15_3 | placeholder | |
| 0x00000140 | ffe_coeff_set15_4 | placeholder | |
| 0x00000144 | 0x00000147 | (Not allocated) | |
| 0x00000148 | ffe_slice_level_set0 | placeholder | |
| 0x0000014c | ffe_slice_level_set1 | placeholder | |
| 0x00000150 | ffe_slice_level_set2 | placeholder | |
| 0x00000154 | ffe_slice_level_set3 | placeholder | |
| 0x00000158 | ffe_slice_level_set4 | placeholder | |
| 0x0000015c | ffe_slice_level_set5 | placeholder | |
| 0x00000160 | ffe_slice_level_set6 | placeholder | |
| 0x00000164 | ffe_slice_level_set7 | placeholder | |
| 0x00000168 | ffe_slice_level_set8 | placeholder | |
| 0x0000016c | ffe_slice_level_set9 | placeholder | |
| 0x00000170 | ffe_slice_level_set10 | placeholder | |
| 0x00000174 | ffe_slice_level_set11 | placeholder | |
| 0x00000178 | ffe_slice_level_set12 | placeholder | |
| 0x0000017c | ffe_slice_level_set13 | placeholder | |
| 0x00000180 | ffe_slice_level_set14 | placeholder | |
| 0x00000184 | ffe_slice_level_set15 | placeholder | |
| 0x00000188 | ffe_err_level_m1m3_set0 | placeholder | |
| 0x0000018c | ffe_err_level_p1p3_set0 | placeholder | |
| 0x00000190 | ffe_err_level_m1m3_set1 | placeholder | |
| 0x00000194 | ffe_err_level_p1p3_set1 | placeholder | |
| 0x00000198 | ffe_err_level_m1m3_set2 | placeholder | |
| 0x0000019c | ffe_err_level_p1p3_set2 | placeholder | |
| 0x000001a0 | ffe_err_level_m1m3_set3 | placeholder | |
| 0x000001a4 | ffe_err_level_p1p3_set3 | placeholder | |
| 0x000001a8 | ffe_err_level_m1m3_set4 | placeholder | |
| 0x000001ac | ffe_err_level_p1p3_set4 | placeholder | |
| 0x000001b0 | ffe_err_level_m1m3_set5 | placeholder | |
| 0x000001b4 | ffe_err_level_p1p3_set5 | placeholder | |
| 0x000001b8 | ffe_err_level_m1m3_set6 | placeholder | |
| 0x000001bc | ffe_err_level_p1p3_set6 | placeholder | |
| 0x000001c0 | ffe_err_level_m1m3_set7 | placeholder | |
| 0x000001c4 | ffe_err_level_p1p3_set7 | placeholder | |
| 0x000001c8 | ffe_err_level_m1m3_set8 | placeholder | |
| 0x000001cc | ffe_err_level_p1p3_set8 | placeholder | |
| 0x000001d0 | ffe_err_level_m1m3_set9 | placeholder | |
| 0x000001d4 | ffe_err_level_p1p3_set9 | placeholder | |
| 0x000001d8 | ffe_err_level_m1m3_set10 | placeholder | |
| 0x000001dc | ffe_err_level_p1p3_set10 | placeholder | |
| 0x000001e0 | ffe_err_level_m1m3_set11 | placeholder | |
| 0x000001e4 | ffe_err_level_p1p3_set11 | placeholder | |
| 0x000001e8 | ffe_err_level_m1m3_set12 | placeholder | |
| 0x000001ec | ffe_err_level_p1p3_set12 | placeholder | |
| 0x000001f0 | ffe_err_level_m1m3_set13 | placeholder | |
| 0x000001f4 | ffe_err_level_p1p3_set13 | placeholder | |
| 0x000001f8 | ffe_err_level_m1m3_set14 | placeholder | |
| 0x000001fc | ffe_err_level_p1p3_set14 | placeholder | |
| 0x00000200 | ffe_err_level_m1m3_set15 | placeholder | |
| 0x00000204 | ffe_err_level_p1p3_set15 | placeholder | |
| 0x00000208 | rx_dump_mem_ctrl | placeholder | |
| 0x0000020c | rx_dump_mem_apb_rd_data | placeholder | |
| 0x00000210 | rx_dump_mem_apb_rd_en | placeholder | |
| 0x00000214 | rx_dump_mem_apb_en | placeholder | |
| 0x00000218 | rx_data_path_control_1 | placeholder | |
| 0x0000021c | adp_msb_lsb_swap_ctrl | placeholder | |
| 0x00000220 | ffe_float_tap_position1 | placeholder | |
| 0x00000224 | ffe_float_tap_position2 | placeholder | |
| 0x00000228 | ffe_float_tap_position3 | placeholder | |
| 0x0000022c | rxeq_clock_gating_ctrl_0 | placeholder | |
| 0x00000230 | rxeq_clock_gating_ctrl_1 | placeholder | |
| 0x00000234 | rxeq_clock_gating_ctrl_2 | placeholder | |
| 0x00000238 | rxeq_clock_gating_ctrl_3 | placeholder | |
| 0x0000023c | rxeq_clock_gating_ctrl_4 | placeholder | |
| 0x00000240 | rxeq_clock_gating_ctrl_6 | placeholder | |
| 0x00000244 | rxeq_clock_gating_ctrl_7 | placeholder | |
| 0x00000248 | rxeq_clock_gating_ctrl_8 | placeholder | |
| 0x0000024c | 0x0000028b | (Not allocated) | |
| 0x0000028c | adc_slicer_level_set0_control | placeholder | |
| 0x00000290 | adc_slicer_level_set1_control | placeholder | |
| 0x00000294 | adc_slicer_level_set2_control | placeholder | |
| 0x00000298 | adc_slicer_level_set3_control | placeholder | |
| 0x0000029c | adc_slicer_level_set4_control | placeholder | |
| 0x000002a0 | adc_slicer_level_set5_control | placeholder | |
| 0x000002a4 | adc_slicer_level_set6_control | placeholder | |
| 0x000002a8 | adc_slicer_level_set7_control | placeholder | |
| 0x000002ac | adc_slicer_level_set8_control | placeholder | |
| 0x000002b0 | adc_slicer_level_set9_control | placeholder | |
| 0x000002b4 | adc_slicer_level_set10_control | placeholder | |
| 0x000002b8 | adc_slicer_level_set11_control | placeholder | |
| 0x000002bc | adc_slicer_level_set12_control | placeholder | |
| 0x000002c0 | adc_slicer_level_set13_control | placeholder | |
| 0x000002c4 | adc_slicer_level_set14_control | placeholder | |
| 0x000002c8 | adc_slicer_level_set15_control | placeholder | |
| 0x000002cc | adc_err_level_set0_control | placeholder | |
| 0x000002d0 | adc_err_level_set1_control | placeholder | |
| 0x000002d4 | adc_err_level_set2_control | placeholder | |
| 0x000002d8 | adc_err_level_set3_control | placeholder | |
| 0x000002dc | adc_err_level_set4_control | placeholder | |
| 0x000002e0 | adc_err_level_set5_control | placeholder | |
| 0x000002e4 | adc_err_level_set6_control | placeholder | |
| 0x000002e8 | adc_err_level_set7_control | placeholder | |
| 0x000002ec | adc_err_level_set8_control | placeholder | |
| 0x000002f0 | adc_err_level_set9_control | placeholder | |
| 0x000002f4 | adc_err_level_set10_control | placeholder | |
| 0x000002f8 | adc_err_level_set11_control | placeholder | |
| 0x000002fc | adc_err_level_set12_control | placeholder | |
| 0x00000300 | adc_err_level_set13_control | placeholder | |
| 0x00000304 | adc_err_level_set14_control | placeholder | |
| 0x00000308 | adc_err_level_set15_control | placeholder | |
| 0x0000030c | rxsararray_valid_calassist_ctrl0 | Rx SAR Array Valid Calibration Assistance Control | |
| 0x00000310 | rxsararray_valid_calassist_ctrl1 | Rx SAR Array Valid Calibration Assistance Control | |
| 0x00000314 | rxsararray_valid_calassist_ctrl2 | Rx SAR Array Valid Calibration Assistance Control | |
| 0x00000318 | rxsararray_valid_calassist_status | Rx SAR Array Valid Calibration Assistance Status | |
| 0x0000031c | rxsar_calassist_ctrl | Rx SAR Calibration Assistance Control | |
| 0x00000320 | rxsar_calassist_status | Rx SAR Calibration Assistance Status | |
| 0x00000324 | 0x000003eb | (Not allocated) | |
| 0x000003ec | main_fsm_control_6 | placeholder | |
| 0x000003f0 | main_fsm_control_0 | placeholder | |
| 0x000003f4 | main_fsm_status_0 | placeholder | |
| 0x000003f8 | main_fsm_control_1 | placeholder | |
| 0x000003fc | main_fsm_control_2 | placeholder | |
| 0x00000400 | main_fsm_control_3 | placeholder | |
| 0x00000404 | taps_set_control | placeholder | |
| 0x00000408 | rx_gearbox_ctrl | Rx Gearbox Control | |
| 0x0000040c | main_fsm_control_4 | placeholder | |
| 0x00000410 | main_fsm_control_5 | placeholder | |
| 0x00000414 | vref_control_1 | placeholder | |
| 0x00000418 | vref_control_2 | placeholder | |
| 0x0000041c | vref_control_3 | placeholder | |
| 0x00000420 | vref_control_4 | placeholder | |
| 0x00000424 | vref_control_5 | placeholder | |
| 0x00000428 | vref_control_6 | placeholder | |
| 0x0000042c | 0x0000042f | (Not allocated) | |
| 0x00000430 | vref_status_0 | placeholder | |
| 0x00000434 | vga_control_6 | placeholder | |
| 0x00000438 | vga_control_5 | placeholder | |
| 0x0000043c | vga_control_4 | placeholder | |
| 0x00000440 | vga_control_0 | placeholder | |
| 0x00000444 | vga_control_1 | placeholder | |
| 0x00000448 | vga_control_2 | placeholder | |
| 0x0000044c | vga_control_3 | placeholder | |
| 0x00000450 | vga_status_0 | placeholder | |
| 0x00000454 | jpp_control_1 | placeholder | |
| 0x00000458 | jpp_control_2 | placeholder | |
| 0x0000045c | 0x0000045f | (Not allocated) | |
| 0x00000460 | ffe_control_0 | placeholder | |
| 0x00000464 | ffe_control_1 | placeholder | |
| 0x00000468 | ffe_control_2 | placeholder | |
| 0x0000046c | ffe_control_3 | placeholder | |
| 0x00000470 | ffe_control_4 | placeholder | |
| 0x00000474 | ffe_control_5 | placeholder | |
| 0x00000478 | 0x0000047b | (Not allocated) | |
| 0x0000047c | ffe_status_0 | placeholder | |
| 0x00000480 | 0x0000048f | (Not allocated) | |
| 0x00000490 | hist_control_0 | placeholder | |
| 0x00000494 | hist_control_1 | placeholder | |
| 0x00000498 | hist_control_2 | placeholder | |
| 0x0000049c | hist_control_3 | placeholder | |
| 0x000004a0 | hist_control_4 | placeholder | |
| 0x000004a4 | hist_control_5 | placeholder | |
| 0x000004a8 | hist_control_6 | placeholder | |
| 0x000004ac | hist_control_7 | placeholder | |
| 0x000004b0 | hist_control_8 | placeholder | |
| 0x000004b4 | hist_control_9 | placeholder | |
| 0x000004b8 | hist_control_10 | placeholder | |
| 0x000004bc | hist_control_11 | placeholder | |
| 0x000004c0 | hist_control_12 | placeholder | |
| 0x000004c4 | hist_control_13 | placeholder | |
| 0x000004c8 | hist_status_0 | placeholder | |
| 0x000004cc | hist_status_1 | placeholder | |
| 0x000004d0 | hist_status_2 | placeholder | |
| 0x000004d4 | hist_status_3 | placeholder | |
| 0x000004d8 | hist_status_4 | placeholder | |
| 0x000004dc | 0x000004df | (Not allocated) | |
| 0x000004e0 | hist_status_5 | placeholder | |
| 0x000004e4 | hist_status_6 | placeholder | |
| 0x000004e8 | hist_status_7 | placeholder | |
| 0x000004ec | hist_status_8 | placeholder | |
| 0x000004f0 | hist_status_9 | placeholder | |
| 0x000004f4 | hist_status_10 | placeholder | |
| 0x000004f8 | hist_status_11 | placeholder | |
| 0x000004fc | hist_status_12 | placeholder | |
| 0x00000500 | hist_status_13 | placeholder | |
| 0x00000504 | 0x0000050f | (Not allocated) | |
| 0x00000510 | hist_status_14 | placeholder | |
| 0x00000514 | hist_status_15 | placeholder | |
| 0x00000518 | ops_control_1 | placeholder | |
| 0x0000051c | ops_control_2 | placeholder | |
| 0x00000520 | ops_control_3 | placeholder | |
| 0x00000524 | ops_control_4 | placeholder | |
| 0x00000528 | 0x0000052b | (Not allocated) | |
| 0x0000052c | ops_status_1 | placeholder | |
| 0x00000530 | 0x00000533 | (Not allocated) | |
| 0x00000534 | ops_status_2 | placeholder | |
| 0x00000538 | adcvref_control_1 | placeholder | |
| 0x0000053c | adcvref_control_2 | placeholder | |
| 0x00000540 | adcvref_control_3 | placeholder | |
| 0x00000544 | adcvref_control_4 | placeholder | |
| 0x00000548 | adcvref_control_5 | placeholder | |
| 0x0000054c | adcvref_control_6 | placeholder | |
| 0x00000550 | adcvref_status_0 | placeholder | |
| 0x00000554 | 0x0000055f | (Not allocated) | |
| 0x00000560 | affe_control_0 | placeholder | |
| 0x00000564 | affe_control_1 | placeholder | |
| 0x00000568 | affe_control_2 | placeholder | |
| 0x0000056c | affe_control_3 | placeholder | |
| 0x00000570 | affe_status_0 | placeholder | |
| 0x00000574 | 0x0000057b | (Not allocated) | |
| 0x0000057c | ofc_control_0 | placeholder | |
| 0x00000580 | ofc_control_1a | placeholder | |
| 0x00000584 | ofc_control_1b | placeholder | |
| 0x00000588 | ofc_control_2 | placeholder | |
| 0x0000058c | ofc_control_3 | placeholder | |
| 0x00000590 | ofc_status_0 | placeholder | |
| 0x00000594 | ffe_coeff_set0_frac_0 | placeholder | |
| 0x00000598 | ffe_coeff_set0_frac_1 | placeholder | |
| 0x0000059c | ffe_coeff_set0_frac_2 | placeholder | |
| 0x000005a0 | ffe_coeff_set0_frac_3 | placeholder | |
| 0x000005a4 | ffe_coeff_set0_frac_4 | placeholder | |
| 0x000005a8 | ffe_coeff_set0_frac_5 | placeholder | |
| 0x000005ac | ffe_coeff_set1_frac_0 | placeholder | |
| 0x000005b0 | ffe_coeff_set1_frac_1 | placeholder | |
| 0x000005b4 | ffe_coeff_set1_frac_2 | placeholder | |
| 0x000005b8 | ffe_coeff_set1_frac_3 | placeholder | |
| 0x000005bc | ffe_coeff_set1_frac_4 | placeholder | |
| 0x000005c0 | ffe_coeff_set1_frac_5 | placeholder | |
| 0x000005c4 | ffe_coeff_set2_frac_0 | placeholder | |
| 0x000005c8 | ffe_coeff_set2_frac_1 | placeholder | |
| 0x000005cc | ffe_coeff_set2_frac_2 | placeholder | |
| 0x000005d0 | ffe_coeff_set2_frac_3 | placeholder | |
| 0x000005d4 | ffe_coeff_set2_frac_4 | placeholder | |
| 0x000005d8 | ffe_coeff_set2_frac_5 | placeholder | |
| 0x000005dc | ffe_coeff_set3_frac_0 | placeholder | |
| 0x000005e0 | ffe_coeff_set3_frac_1 | placeholder | |
| 0x000005e4 | ffe_coeff_set3_frac_2 | placeholder | |
| 0x000005e8 | ffe_coeff_set3_frac_3 | placeholder | |
| 0x000005ec | ffe_coeff_set3_frac_4 | placeholder | |
| 0x000005f0 | ffe_coeff_set3_frac_5 | placeholder | |
| 0x000005f4 | ffe_coeff_set4_frac_0 | placeholder | |
| 0x000005f8 | ffe_coeff_set4_frac_1 | placeholder | |
| 0x000005fc | ffe_coeff_set4_frac_2 | placeholder | |
| 0x00000600 | ffe_coeff_set4_frac_3 | placeholder | |
| 0x00000604 | ffe_coeff_set4_frac_4 | placeholder | |
| 0x00000608 | ffe_coeff_set4_frac_5 | placeholder | |
| 0x0000060c | ffe_coeff_set5_frac_0 | placeholder | |
| 0x00000610 | ffe_coeff_set5_frac_1 | placeholder | |
| 0x00000614 | ffe_coeff_set5_frac_2 | placeholder | |
| 0x00000618 | ffe_coeff_set5_frac_3 | placeholder | |
| 0x0000061c | ffe_coeff_set5_frac_4 | placeholder | |
| 0x00000620 | ffe_coeff_set5_frac_5 | placeholder | |
| 0x00000624 | ffe_coeff_set6_frac_0 | placeholder | |
| 0x00000628 | ffe_coeff_set6_frac_1 | placeholder | |
| 0x0000062c | ffe_coeff_set6_frac_2 | placeholder | |
| 0x00000630 | ffe_coeff_set6_frac_3 | placeholder | |
| 0x00000634 | ffe_coeff_set6_frac_4 | placeholder | |
| 0x00000638 | ffe_coeff_set6_frac_5 | placeholder | |
| 0x0000063c | ffe_coeff_set7_frac_0 | placeholder | |
| 0x00000640 | ffe_coeff_set7_frac_1 | placeholder | |
| 0x00000644 | ffe_coeff_set7_frac_2 | placeholder | |
| 0x00000648 | ffe_coeff_set7_frac_3 | placeholder | |
| 0x0000064c | ffe_coeff_set7_frac_4 | placeholder | |
| 0x00000650 | ffe_coeff_set7_frac_5 | placeholder | |
| 0x00000654 | ffe_coeff_set8_frac_0 | placeholder | |
| 0x00000658 | ffe_coeff_set8_frac_1 | placeholder | |
| 0x0000065c | ffe_coeff_set8_frac_2 | placeholder | |
| 0x00000660 | ffe_coeff_set8_frac_3 | placeholder | |
| 0x00000664 | ffe_coeff_set8_frac_4 | placeholder | |
| 0x00000668 | ffe_coeff_set8_frac_5 | placeholder | |
| 0x0000066c | ffe_coeff_set9_frac_0 | placeholder | |
| 0x00000670 | ffe_coeff_set9_frac_1 | placeholder | |
| 0x00000674 | ffe_coeff_set9_frac_2 | placeholder | |
| 0x00000678 | ffe_coeff_set9_frac_3 | placeholder | |
| 0x0000067c | ffe_coeff_set9_frac_4 | placeholder | |
| 0x00000680 | ffe_coeff_set9_frac_5 | placeholder | |
| 0x00000684 | ffe_coeff_set10_frac_0 | placeholder | |
| 0x00000688 | ffe_coeff_set10_frac_1 | placeholder | |
| 0x0000068c | ffe_coeff_set10_frac_2 | placeholder | |
| 0x00000690 | ffe_coeff_set10_frac_3 | placeholder | |
| 0x00000694 | ffe_coeff_set10_frac_4 | placeholder | |
| 0x00000698 | ffe_coeff_set10_frac_5 | placeholder | |
| 0x0000069c | ffe_coeff_set11_frac_0 | placeholder | |
| 0x000006a0 | ffe_coeff_set11_frac_1 | placeholder | |
| 0x000006a4 | ffe_coeff_set11_frac_2 | placeholder | |
| 0x000006a8 | ffe_coeff_set11_frac_3 | placeholder | |
| 0x000006ac | ffe_coeff_set11_frac_4 | placeholder | |
| 0x000006b0 | ffe_coeff_set11_frac_5 | placeholder | |
| 0x000006b4 | ffe_coeff_set12_frac_0 | placeholder | |
| 0x000006b8 | ffe_coeff_set12_frac_1 | placeholder | |
| 0x000006bc | ffe_coeff_set12_frac_2 | placeholder | |
| 0x000006c0 | ffe_coeff_set12_frac_3 | placeholder | |
| 0x000006c4 | ffe_coeff_set12_frac_4 | placeholder | |
| 0x000006c8 | ffe_coeff_set12_frac_5 | placeholder | |
| 0x000006cc | ffe_coeff_set13_frac_0 | placeholder | |
| 0x000006d0 | ffe_coeff_set13_frac_1 | placeholder | |
| 0x000006d4 | ffe_coeff_set13_frac_2 | placeholder | |
| 0x000006d8 | ffe_coeff_set13_frac_3 | placeholder | |
| 0x000006dc | ffe_coeff_set13_frac_4 | placeholder | |
| 0x000006e0 | ffe_coeff_set13_frac_5 | placeholder | |
| 0x000006e4 | ffe_coeff_set14_frac_0 | placeholder | |
| 0x000006e8 | ffe_coeff_set14_frac_1 | placeholder | |
| 0x000006ec | ffe_coeff_set14_frac_2 | placeholder | |
| 0x000006f0 | ffe_coeff_set14_frac_3 | placeholder | |
| 0x000006f4 | ffe_coeff_set14_frac_4 | placeholder | |
| 0x000006f8 | ffe_coeff_set14_frac_5 | placeholder | |
| 0x000006fc | ffe_coeff_set15_frac_0 | placeholder | |
| 0x00000700 | ffe_coeff_set15_frac_1 | placeholder | |
| 0x00000704 | ffe_coeff_set15_frac_2 | placeholder | |
| 0x00000708 | ffe_coeff_set15_frac_3 | placeholder | |
| 0x0000070c | ffe_coeff_set15_frac_4 | placeholder | |
| 0x00000710 | ffe_coeff_set15_frac_5 | placeholder | |
| 0x00000714 | ffe_err_level_frac_set0_0 | placeholder | |
| 0x00000718 | ffe_err_level_frac_set1_0 | placeholder | |
| 0x0000071c | ffe_err_level_frac_set2_0 | placeholder | |
| 0x00000720 | ffe_err_level_frac_set3_0 | placeholder | |
| 0x00000724 | ffe_err_level_frac_set4_0 | placeholder | |
| 0x00000728 | ffe_err_level_frac_set5_0 | placeholder | |
| 0x0000072c | ffe_err_level_frac_set6_0 | placeholder | |
| 0x00000730 | ffe_err_level_frac_set7_0 | placeholder | |
| 0x00000734 | ffe_err_level_frac_set8_0 | placeholder | |
| 0x00000738 | ffe_err_level_frac_set9_0 | placeholder | |
| 0x0000073c | ffe_err_level_frac_set10_0 | placeholder | |
| 0x00000740 | ffe_err_level_frac_set11_0 | placeholder | |
| 0x00000744 | ffe_err_level_frac_set12_0 | placeholder | |
| 0x00000748 | ffe_err_level_frac_set13_0 | placeholder | |
| 0x0000074c | ffe_err_level_frac_set14_0 | placeholder | |
| 0x00000750 | ffe_err_level_frac_set15_0 | placeholder | |
| 0x00000754 | adc_err_level_frac_set0_0 | placeholder | |
| 0x00000758 | adc_err_level_frac_set1_0 | placeholder | |
| 0x0000075c | adc_err_level_frac_set2_0 | placeholder | |
| 0x00000760 | adc_err_level_frac_set3_0 | placeholder | |
| 0x00000764 | adc_err_level_frac_set4_0 | placeholder | |
| 0x00000768 | adc_err_level_frac_set5_0 | placeholder | |
| 0x0000076c | adc_err_level_frac_set6_0 | placeholder | |
| 0x00000770 | adc_err_level_frac_set7_0 | placeholder | |
| 0x00000774 | adc_err_level_frac_set8_0 | placeholder | |
| 0x00000778 | adc_err_level_frac_set9_0 | placeholder | |
| 0x0000077c | adc_err_level_frac_set10_0 | placeholder | |
| 0x00000780 | adc_err_level_frac_set11_0 | placeholder | |
| 0x00000784 | adc_err_level_frac_set12_0 | placeholder | |
| 0x00000788 | adc_err_level_frac_set13_0 | placeholder | |
| 0x0000078c | adc_err_level_frac_set14_0 | placeholder | |
| 0x00000790 | adc_err_level_frac_set15_0 | placeholder | |
| 0x00000794 | affe_lms_set0 | placeholder | |
| 0x00000798 | affe_lms_set1 | placeholder | |
| 0x0000079c | affe_lms_set2 | placeholder | |
| 0x000007a0 | affe_lms_set3 | placeholder | |
| 0x000007a4 | affe_lms_set4 | placeholder | |
| 0x000007a8 | affe_lms_set5 | placeholder | |
| 0x000007ac | affe_lms_set6 | placeholder | |
| 0x000007b0 | affe_lms_set7 | placeholder | |
| 0x000007b4 | affe_lms_set8 | placeholder | |
| 0x000007b8 | affe_lms_set9 | placeholder | |
| 0x000007bc | affe_lms_set10 | placeholder | |
| 0x000007c0 | affe_lms_set11 | placeholder | |
| 0x000007c4 | affe_lms_set12 | placeholder | |
| 0x000007c8 | affe_lms_set13 | placeholder | |
| 0x000007cc | affe_lms_set14 | placeholder | |
| 0x000007d0 | affe_lms_set15 | placeholder | |
| 0x000007d4 | affe_lms_frac_set0 | placeholder | |
| 0x000007d8 | affe_lms_frac_set1 | placeholder | |
| 0x000007dc | affe_lms_frac_set2 | placeholder | |
| 0x000007e0 | affe_lms_frac_set3 | placeholder | |
| 0x000007e4 | affe_lms_frac_set4 | placeholder | |
| 0x000007e8 | affe_lms_frac_set5 | placeholder | |
| 0x000007ec | affe_lms_frac_set6 | placeholder | |
| 0x000007f0 | affe_lms_frac_set7 | placeholder | |
| 0x000007f4 | affe_lms_frac_set8 | placeholder | |
| 0x000007f8 | affe_lms_frac_set9 | placeholder | |
| 0x000007fc | affe_lms_frac_set10 | placeholder | |
| 0x00000800 | affe_lms_frac_set11 | placeholder | |
| 0x00000804 | affe_lms_frac_set12 | placeholder | |
| 0x00000808 | affe_lms_frac_set13 | placeholder | |
| 0x0000080c | affe_lms_frac_set14 | placeholder | |
| 0x00000810 | affe_lms_frac_set15 | placeholder | |
| 0x00000814 | saturation_status_0 | placeholder | |
| 0x00000818 | saturation_status_1 | placeholder | |
| 0x0000081c | 0x0000081f | (Not allocated) | |
| 0x00000820 | saturation_status_3 | placeholder | |
| 0x00000824 | zeroavg_status_0 | placeholder | |
| 0x00000828 | zeroavg_status_1 | placeholder | |
| 0x0000082c | 0x0000082f | (Not allocated) | |
| 0x00000830 | zeroavg_status_3 | placeholder | |
| 0x00000834 | adcofc_control_0 | placeholder | |
| 0x00000838 | adcofc_control_1 | placeholder | |
| 0x0000083c | adcofc_control_2 | placeholder | |
| 0x00000840 | adcofc_control_3 | placeholder | |
| 0x00000844 | adcofc_status_0 | placeholder | |
| 0x00000848 | edg_slice_control_0 | placeholder | |
| 0x0000084c | edg_slicer_level_set0_control | placeholder | |
| 0x00000850 | edg_slicer_level_set1_control | placeholder | |
| 0x00000854 | edg_slicer_level_set2_control | placeholder | |
| 0x00000858 | edg_slicer_level_set3_control | placeholder | |
| 0x0000085c | edg_slicer_level_set4_control | placeholder | |
| 0x00000860 | edg_slicer_level_set5_control | placeholder | |
| 0x00000864 | edg_slicer_level_set6_control | placeholder | |
| 0x00000868 | edg_slicer_level_set7_control | placeholder | |
| 0x0000086c | edgvref_control_1 | placeholder | |
| 0x00000870 | edgvref_control_2 | placeholder | |
| 0x00000874 | edgvref_control_3 | placeholder | |
| 0x00000878 | edgvref_control_4 | placeholder | |
| 0x0000087c | edgvref_control_5 | placeholder | |
| 0x00000880 | edgvref_control_6 | placeholder | |
| 0x00000884 | edgvref_frac_set0 | placeholder | |
| 0x00000888 | edgvref_frac_set1 | placeholder | |
| 0x0000088c | edgvref_frac_set2 | placeholder | |
| 0x00000890 | edgvref_frac_set3 | placeholder | |
| 0x00000894 | edgvref_frac_set4 | placeholder | |
| 0x00000898 | edgvref_frac_set5 | placeholder | |
| 0x0000089c | edgvref_frac_set6 | placeholder | |
| 0x000008a0 | edgvref_frac_set7 | placeholder | |
| 0x000008a4 | jpp_control_0 | placeholder | |
| 0x000008a8 | dfe_lms_control_0 | placeholder | |
| 0x000008ac | dfe_lms_control_1 | placeholder | |
| 0x000008b0 | dfe_lms_control_2 | placeholder | |
| 0x000008b4 | dfe_lms_control_3 | placeholder | |
| 0x000008b8 | dfe_lms_status_0 | placeholder | |
| 0x000008bc | dfe_lms_set0to3 | placeholder | |
| 0x000008c0 | dfe_lms_set4to7 | placeholder | |
| 0x000008c4 | dfe_lms_set8to11 | placeholder | |
| 0x000008c8 | dfe_lms_set12to15 | placeholder | |
| 0x000008cc | dfe_lms_frac_set0to3 | placeholder | |
| 0x000008d0 | dfe_lms_frac_set4to7 | placeholder | |
| 0x000008d4 | dfe_lms_frac_set8to11 | placeholder | |
| 0x000008d8 | dfe_lms_frac_set12to15 | placeholder | |
| 0x000008dc | dfe_control_0 | placeholder | |
| 0x000008e0 | rx_sararray_valid_0 | Rx SAR Array valid | |
| 0x000008e4 | rx_sararray_valid_1 | Rx SAR Array valid | |
| 0x000008e8 | cdr_ffe_pre1_set0to3 | Rx SAR Array valid | |
| 0x000008ec | cdr_ffe_pre1_set4to7 | Rx SAR Array valid | |
| 0x000008f0 | cdr_ffe_pre1_set8to11 | Rx SAR Array valid | |
| 0x000008f4 | cdr_ffe_pre1_set12to15 | Rx SAR Array valid | |
| 0x000008f8 | cdr_ffe_slicer_level_set0_control | placeholder | |
| 0x000008fc | cdr_ffe_slicer_level_set1_control | placeholder | |
| 0x00000900 | cdr_ffe_slicer_level_set2_control | placeholder | |
| 0x00000904 | cdr_ffe_slicer_level_set3_control | placeholder | |
| 0x00000908 | 0x0000090b | (Not allocated) | |
| 0x0000090c | cdr_ffe_slicer_level_set4_control | placeholder | |
| 0x00000910 | cdr_ffe_slicer_level_set5_control | placeholder | |
| 0x00000914 | cdr_ffe_slicer_level_set6_control | placeholder | |
| 0x00000918 | cdr_ffe_slicer_level_set7_control | placeholder | |
| 0x0000091c | cdr_ffe_slicer_level_set8_control | placeholder | |
| 0x00000920 | cdr_ffe_slicer_level_set9_control | placeholder | |
| 0x00000924 | cdr_ffe_slicer_level_set10_control | placeholder | |
| 0x00000928 | cdr_ffe_slicer_level_set11_control | placeholder | |
| 0x0000092c | cdr_ffe_slicer_level_set12_control | placeholder | |
| 0x00000930 | cdr_ffe_slicer_level_set13_control | placeholder | |
| 0x00000934 | cdr_ffe_slicer_level_set14_control | placeholder | |
| 0x00000938 | cdr_ffe_slicer_level_set15_control | placeholder | |
| 0x0000093c | 0x0000093f | (Not allocated) | |
| 0x00000940 | cdr_ffe_err_level_m1m3_set0 | placeholder | |
| 0x00000944 | cdr_ffe_err_level_p1p3_set0 | placeholder | |
| 0x00000948 | cdr_ffe_err_level_m1m3_set1 | placeholder | |
| 0x0000094c | cdr_ffe_err_level_p1p3_set1 | placeholder | |
| 0x00000950 | cdr_ffe_err_level_m1m3_set2 | placeholder | |
| 0x00000954 | cdr_ffe_err_level_p1p3_set2 | placeholder | |
| 0x00000958 | cdr_ffe_err_level_m1m3_set3 | placeholder | |
| 0x0000095c | cdr_ffe_err_level_p1p3_set3 | placeholder | |
| 0x00000960 | cdr_ffe_err_level_m1m3_set4 | placeholder | |
| 0x00000964 | cdr_ffe_err_level_p1p3_set4 | placeholder | |
| 0x00000968 | cdr_ffe_err_level_m1m3_set5 | placeholder | |
| 0x0000096c | cdr_ffe_err_level_p1p3_set5 | placeholder | |
| 0x00000970 | cdr_ffe_err_level_m1m3_set6 | placeholder | |
| 0x00000974 | cdr_ffe_err_level_p1p3_set6 | placeholder | |
| 0x00000978 | cdr_ffe_err_level_m1m3_set7 | placeholder | |
| 0x0000097c | cdr_ffe_err_level_p1p3_set7 | placeholder | |
| 0x00000980 | cdr_ffe_err_level_m1m3_set8 | placeholder | |
| 0x00000984 | cdr_ffe_err_level_p1p3_set8 | placeholder | |
| 0x00000988 | cdr_ffe_err_level_m1m3_set9 | placeholder | |
| 0x0000098c | cdr_ffe_err_level_p1p3_set9 | placeholder | |
| 0x00000990 | cdr_ffe_err_level_m1m3_set10 | placeholder | |
| 0x00000994 | cdr_ffe_err_level_p1p3_set10 | placeholder | |
| 0x00000998 | cdr_ffe_err_level_m1m3_set11 | placeholder | |
| 0x0000099c | cdr_ffe_err_level_p1p3_set11 | placeholder | |
| 0x000009a0 | cdr_ffe_err_level_m1m3_set12 | placeholder | |
| 0x000009a4 | cdr_ffe_err_level_p1p3_set12 | placeholder | |
| 0x000009a8 | cdr_ffe_err_level_m1m3_set13 | placeholder | |
| 0x000009ac | cdr_ffe_err_level_p1p3_set13 | placeholder | |
| 0x000009b0 | cdr_ffe_err_level_m1m3_set14 | placeholder | |
| 0x000009b4 | cdr_ffe_err_level_p1p3_set14 | placeholder | |
| 0x000009b8 | cdr_ffe_err_level_m1m3_set15 | placeholder | |
| 0x000009bc | 0x000009bf | (Not allocated) | |
| 0x000009c0 | cdr_ffe_err_level_p1p3_set15 | placeholder | |
| 0x000009c4 | 0x000009c7 | (Not allocated) | |
| 0x000009c8 | cdr_ffe_post1_set0to3 | Rx SAR Array valid | |
| 0x000009cc | cdr_ffe_post1_set4to7 | Rx SAR Array valid | |
| 0x000009d0 | cdr_ffe_post1_set8to11 | Rx SAR Array valid | |
| 0x000009d4 | cdr_ffe_post1_set12to15 | Rx SAR Array valid | |
| 0x000009d8 | cdr_ffe_control_0 | placeholder | |
| 0x000009dc | cdr_ffe_control_1 | placeholder | |
| 0x000009e0 | cdr_ffe_control_2 | placeholder | |
| 0x000009e4 | lms_avg_updn_status_0 | placeholder | |
| 0x000009e8 | cdr_ffe_vref_control_1 | placeholder | |
| 0x000009ec | cdr_ffe_vref_control_2 | placeholder | |
| 0x000009f0 | cdr_ffe_vref_control_3 | placeholder | |
| 0x000009f4 | cdr_ffe_vref_control_4 | placeholder | |
| 0x000009f8 | cdr_ffe_vref_control_5 | placeholder | |
| 0x000009fc | cdr_ffe_vref_control_6 | placeholder | |
| 0x00000a00 | 0x00000a03 | (Not allocated) | |
| 0x00000a04 | cdr_ffe_ofc_control_0 | placeholder | |
| 0x00000a08 | cdr_ffe_ofc_control_1a | placeholder | |
| 0x00000a0c | cdr_ffe_ofc_control_1b | placeholder | |
| 0x00000a10 | cdr_ffe_ofc_control_2 | placeholder | |
| 0x00000a14 | cdr_ffe_ofc_control_3 | placeholder | |
| 0x00000a18 | cdr_ffe_ofc_status_0 | placeholder | |
| 0x00000a1c | cdr_ffe_pre1_set0to3_frac | Rx SAR Array valid | |
| 0x00000a20 | cdr_ffe_pre1_set4to7_frac | Rx SAR Array valid | |
| 0x00000a24 | cdr_ffe_pre1_set8to11_frac | Rx SAR Array valid | |
| 0x00000a28 | cdr_ffe_pre1_set12to15_frac | Rx SAR Array valid | |
| 0x00000a2c | cdr_ffe_post1_set0to3_frac | Rx SAR Array valid | |
| 0x00000a30 | cdr_ffe_post1_set4to7_frac | Rx SAR Array valid | |
| 0x00000a34 | cdr_ffe_post1_set8to11_frac | Rx SAR Array valid | |
| 0x00000a38 | cdr_ffe_post1_set12to15_frac | Rx SAR Array valid | |
| 0x00000a3c | cdr_ffe_err_level_frac_set0_0 | placeholder | |
| 0x00000a40 | cdr_ffe_err_level_frac_set1_0 | placeholder | |
| 0x00000a44 | cdr_ffe_err_level_frac_set2_0 | placeholder | |
| 0x00000a48 | cdr_ffe_err_level_frac_set3_0 | placeholder | |
| 0x00000a4c | cdr_ffe_err_level_frac_set4_0 | placeholder | |
| 0x00000a50 | cdr_ffe_err_level_frac_set5_0 | placeholder | |
| 0x00000a54 | cdr_ffe_err_level_frac_set6_0 | placeholder | |
| 0x00000a58 | cdr_ffe_err_level_frac_set7_0 | placeholder | |
| 0x00000a5c | cdr_ffe_err_level_frac_set8_0 | placeholder | |
| 0x00000a60 | cdr_ffe_err_level_frac_set9_0 | placeholder | |
| 0x00000a64 | cdr_ffe_err_level_frac_set10_0 | placeholder | |
| 0x00000a68 | cdr_ffe_err_level_frac_set11_0 | placeholder | |
| 0x00000a6c | cdr_ffe_err_level_frac_set12_0 | placeholder | |
| 0x00000a70 | cdr_ffe_err_level_frac_set13_0 | placeholder | |
| 0x00000a74 | cdr_ffe_err_level_frac_set14_0 | placeholder | |
| 0x00000a78 | cdr_ffe_err_level_frac_set15_0 | placeholder | |
| 0x00000a7c | cdr_ffe_control_3 | placeholder | |
| 0x00000a80 | cdr_ffe_pre3_set0to3 | Rx SAR Array valid | |
| 0x00000a84 | cdr_ffe_pre3_set4to7 | Rx SAR Array valid | |
| 0x00000a88 | cdr_ffe_pre3_set8to11 | Rx SAR Array valid | |
| 0x00000a8c | cdr_ffe_pre3_set12to15 | Rx SAR Array valid | |
| 0x00000a90 | cdr_ffe_pre2_set0to3 | Rx SAR Array valid | |
| 0x00000a94 | cdr_ffe_pre2_set4to7 | Rx SAR Array valid | |
| 0x00000a98 | cdr_ffe_pre2_set8to11 | Rx SAR Array valid | |
| 0x00000a9c | cdr_ffe_pre2_set12to15 | Rx SAR Array valid | |
| 0x00000aa0 | cdr_ffe_post2_set0to3 | Rx SAR Array valid | |
| 0x00000aa4 | cdr_ffe_post2_set4to7 | Rx SAR Array valid | |
| 0x00000aa8 | cdr_ffe_post2_set8to11 | Rx SAR Array valid | |
| 0x00000aac | cdr_ffe_post2_set12to15 | Rx SAR Array valid | |
| 0x00000ab0 | cdr_ffe_post3_set0to3 | Rx SAR Array valid | |
| 0x00000ab4 | cdr_ffe_post3_set4to7 | Rx SAR Array valid | |
| 0x00000ab8 | cdr_ffe_post3_set8to11 | Rx SAR Array valid | |
| 0x00000abc | cdr_ffe_post3_set12to15 | Rx SAR Array valid | |
| 0x00000ac0 | cdr_ffe_post4_set0to3 | Rx SAR Array valid | |
| 0x00000ac4 | cdr_ffe_post4_set4to7 | Rx SAR Array valid | |
| 0x00000ac8 | cdr_ffe_post4_set8to11 | Rx SAR Array valid | |
| 0x00000acc | cdr_ffe_post4_set12to15 | Rx SAR Array valid | |
| 0x00000ad0 | cdr_ffe_pre3_set0to3_frac | Rx SAR Array valid | |
| 0x00000ad4 | cdr_ffe_pre3_set4to7_frac | Rx SAR Array valid | |
| 0x00000ad8 | cdr_ffe_pre3_set8to11_frac | Rx SAR Array valid | |
| 0x00000adc | cdr_ffe_pre3_set12to15_frac | Rx SAR Array valid | |
| 0x00000ae0 | cdr_ffe_pre2_set0to3_frac | Rx SAR Array valid | |
| 0x00000ae4 | cdr_ffe_pre2_set4to7_frac | Rx SAR Array valid | |
| 0x00000ae8 | cdr_ffe_pre2_set8to11_frac | Rx SAR Array valid | |
| 0x00000aec | cdr_ffe_pre2_set12to15_frac | Rx SAR Array valid | |
| 0x00000af0 | cdr_ffe_post2_set0to3_frac | Rx SAR Array valid | |
| 0x00000af4 | cdr_ffe_post2_set4to7_frac | Rx SAR Array valid | |
| 0x00000af8 | cdr_ffe_post2_set8to11_frac | Rx SAR Array valid | |
| 0x00000afc | cdr_ffe_post2_set12to15_frac | Rx SAR Array valid | |
| 0x00000b00 | cdr_ffe_post3_set0to3_frac | Rx SAR Array valid | |
| 0x00000b04 | cdr_ffe_post3_set4to7_frac | Rx SAR Array valid | |
| 0x00000b08 | cdr_ffe_post3_set8to11_frac | Rx SAR Array valid | |
| 0x00000b0c | cdr_ffe_post3_set12to15_frac | Rx SAR Array valid | |
| 0x00000b10 | cdr_ffe_post4_set0to3_frac | Rx SAR Array valid | |
| 0x00000b14 | cdr_ffe_post4_set4to7_frac | Rx SAR Array valid | |
| 0x00000b18 | cdr_ffe_post4_set8to11_frac | Rx SAR Array valid | |
| 0x00000b1c | cdr_ffe_post4_set12to15_frac | Rx SAR Array valid | |
| 0x00000b20 | saturation_status_4 | placeholder | |
| 0x00000b24 | affe_if_control_0 | placeholder | |
| 0x00000b28 | ops_taps_b0_sar_0to3 | placeholder | |
| 0x00000b2c | ops_taps_b0_sar_4to7 | placeholder | |
| 0x00000b30 | ops_taps_b0_sar_8to11 | placeholder | |
| 0x00000b34 | ops_taps_b0_sar_12to15 | placeholder | |
| 0x00000b38 | ops_taps_b0_sar_16to19 | placeholder | |
| 0x00000b3c | ops_taps_b0_sar_20to23 | placeholder | |
| 0x00000b40 | ops_taps_b0_sar_24to27 | placeholder | |
| 0x00000b44 | ops_taps_b0_sar_28to31 | placeholder | |
| 0x00000b48 | ops_taps_b0_sar_32to35 | placeholder | |
| 0x00000b4c | ops_taps_b0_sar_36to39 | placeholder | |
| 0x00000b50 | ops_taps_b0_sar_40to43 | placeholder | |
| 0x00000b54 | ops_taps_b0_sar_44to47 | placeholder | |
| 0x00000b58 | ops_taps_b0_sar_48to51 | placeholder | |
| 0x00000b5c | ops_taps_b0_sar_52to55 | placeholder | |
| 0x00000b60 | ops_taps_b0_sar_56to59 | placeholder | |
| 0x00000b64 | ops_taps_b0_sar_60to63 | placeholder | |
| 0x00000b68 | ops_taps_b1_sar_0to3 | placeholder | |
| 0x00000b6c | ops_taps_b1_sar_4to7 | placeholder | |
| 0x00000b70 | ops_taps_b1_sar_8to11 | placeholder | |
| 0x00000b74 | ops_taps_b1_sar_12to15 | placeholder | |
| 0x00000b78 | ops_taps_b1_sar_16to19 | placeholder | |
| 0x00000b7c | ops_taps_b1_sar_20to23 | placeholder | |
| 0x00000b80 | ops_taps_b1_sar_24to27 | placeholder | |
| 0x00000b84 | ops_taps_b1_sar_28to31 | placeholder | |
| 0x00000b88 | ops_taps_b1_sar_32to35 | placeholder | |
| 0x00000b8c | ops_taps_b1_sar_36to39 | placeholder | |
| 0x00000b90 | ops_taps_b1_sar_40to43 | placeholder | |
| 0x00000b94 | ops_taps_b1_sar_44to47 | placeholder | |
| 0x00000b98 | ops_taps_b1_sar_48to51 | placeholder | |
| 0x00000b9c | ops_taps_b1_sar_52to55 | placeholder | |
| 0x00000ba0 | ops_taps_b1_sar_56to59 | placeholder | |
| 0x00000ba4 | ops_taps_b1_sar_60to63 | placeholder | |
| 0x00000ba8 | ops_taps_b2_sar_0to3 | placeholder | |
| 0x00000bac | ops_taps_b2_sar_4to7 | placeholder | |
| 0x00000bb0 | ops_taps_b2_sar_8to11 | placeholder | |
| 0x00000bb4 | ops_taps_b2_sar_12to15 | placeholder | |
| 0x00000bb8 | ops_taps_b2_sar_16to19 | placeholder | |
| 0x00000bbc | ops_taps_b2_sar_20to23 | placeholder | |
| 0x00000bc0 | ops_taps_b2_sar_24to27 | placeholder | |
| 0x00000bc4 | ops_taps_b2_sar_28to31 | placeholder | |
| 0x00000bc8 | ops_taps_b2_sar_32to35 | placeholder | |
| 0x00000bcc | ops_taps_b2_sar_36to39 | placeholder | |
| 0x00000bd0 | ops_taps_b2_sar_40to43 | placeholder | |
| 0x00000bd4 | ops_taps_b2_sar_44to47 | placeholder | |
| 0x00000bd8 | ops_taps_b2_sar_48to51 | placeholder | |
| 0x00000bdc | ops_taps_b2_sar_52to55 | placeholder | |
| 0x00000be0 | ops_taps_b2_sar_56to59 | placeholder | |
| 0x00000be4 | ops_taps_b2_sar_60to63 | placeholder | |
| 0x00000be8 | ops_taps_b3_sar_0to3 | placeholder | |
| 0x00000bec | ops_taps_b3_sar_4to7 | placeholder | |
| 0x00000bf0 | ops_taps_b3_sar_8to11 | placeholder | |
| 0x00000bf4 | ops_taps_b3_sar_12to15 | placeholder | |
| 0x00000bf8 | ops_taps_b3_sar_16to19 | placeholder | |
| 0x00000bfc | ops_taps_b3_sar_20to23 | placeholder | |
| 0x00000c00 | ops_taps_b3_sar_24to27 | placeholder | |
| 0x00000c04 | ops_taps_b3_sar_28to31 | placeholder | |
| 0x00000c08 | ops_taps_b3_sar_32to35 | placeholder | |
| 0x00000c0c | ops_taps_b3_sar_36to39 | placeholder | |
| 0x00000c10 | ops_taps_b3_sar_40to43 | placeholder | |
| 0x00000c14 | ops_taps_b3_sar_44to47 | placeholder | |
| 0x00000c18 | ops_taps_b3_sar_48to51 | placeholder | |
| 0x00000c1c | ops_taps_b3_sar_52to55 | placeholder | |
| 0x00000c20 | ops_taps_b3_sar_56to59 | placeholder | |
| 0x00000c24 | ops_taps_b3_sar_60to63 | placeholder | |
| 0x00000c28 | ops_taps_b4_sar_0to3 | placeholder | |
| 0x00000c2c | ops_taps_b4_sar_4to7 | placeholder | |
| 0x00000c30 | ops_taps_b4_sar_8to11 | placeholder | |
| 0x00000c34 | ops_taps_b4_sar_12to15 | placeholder | |
| 0x00000c38 | ops_taps_b4_sar_16to19 | placeholder | |
| 0x00000c3c | ops_taps_b4_sar_20to23 | placeholder | |
| 0x00000c40 | ops_taps_b4_sar_24to27 | placeholder | |
| 0x00000c44 | ops_taps_b4_sar_28to31 | placeholder | |
| 0x00000c48 | ops_taps_b4_sar_32to35 | placeholder | |
| 0x00000c4c | ops_taps_b4_sar_36to39 | placeholder | |
| 0x00000c50 | ops_taps_b4_sar_40to43 | placeholder | |
| 0x00000c54 | ops_taps_b4_sar_44to47 | placeholder | |
| 0x00000c58 | ops_taps_b4_sar_48to51 | placeholder | |
| 0x00000c5c | ops_taps_b4_sar_52to55 | placeholder | |
| 0x00000c60 | ops_taps_b4_sar_56to59 | placeholder | |
| 0x00000c64 | ops_taps_b4_sar_60to63 | placeholder | |
| 0x00000c68 | ops_taps_b5_sar_0to3 | placeholder | |
| 0x00000c6c | ops_taps_b5_sar_4to7 | placeholder | |
| 0x00000c70 | ops_taps_b5_sar_8to11 | placeholder | |
| 0x00000c74 | ops_taps_b5_sar_12to15 | placeholder | |
| 0x00000c78 | ops_taps_b5_sar_16to19 | placeholder | |
| 0x00000c7c | ops_taps_b5_sar_20to23 | placeholder | |
| 0x00000c80 | ops_taps_b5_sar_24to27 | placeholder | |
| 0x00000c84 | ops_taps_b5_sar_28to31 | placeholder | |
| 0x00000c88 | ops_taps_b5_sar_32to35 | placeholder | |
| 0x00000c8c | ops_taps_b5_sar_36to39 | placeholder | |
| 0x00000c90 | ops_taps_b5_sar_40to43 | placeholder | |
| 0x00000c94 | ops_taps_b5_sar_44to47 | placeholder | |
| 0x00000c98 | ops_taps_b5_sar_48to51 | placeholder | |
| 0x00000c9c | ops_taps_b5_sar_52to55 | placeholder | |
| 0x00000ca0 | ops_taps_b5_sar_56to59 | placeholder | |
| 0x00000ca4 | ops_taps_b5_sar_60to63 | placeholder | |
| 0x00000ca8 | ops_taps_fra_b0_sar_0to3 | placeholder | |
| 0x00000cac | ops_taps_fra_b0_sar_4to7 | placeholder | |
| 0x00000cb0 | ops_taps_fra_b0_sar_8to11 | placeholder | |
| 0x00000cb4 | ops_taps_fra_b0_sar_12to15 | placeholder | |
| 0x00000cb8 | ops_taps_fra_b0_sar_16to19 | placeholder | |
| 0x00000cbc | ops_taps_fra_b0_sar_20to23 | placeholder | |
| 0x00000cc0 | ops_taps_fra_b0_sar_24to27 | placeholder | |
| 0x00000cc4 | ops_taps_fra_b0_sar_28to31 | placeholder | |
| 0x00000cc8 | ops_taps_fra_b0_sar_32to35 | placeholder | |
| 0x00000ccc | ops_taps_fra_b0_sar_36to39 | placeholder | |
| 0x00000cd0 | ops_taps_fra_b0_sar_40to43 | placeholder | |
| 0x00000cd4 | ops_taps_fra_b0_sar_44to47 | placeholder | |
| 0x00000cd8 | ops_taps_fra_b0_sar_48to51 | placeholder | |
| 0x00000cdc | ops_taps_fra_b0_sar_52to55 | placeholder | |
| 0x00000ce0 | ops_taps_fra_b0_sar_56to59 | placeholder | |
| 0x00000ce4 | ops_taps_fra_b0_sar_60to63 | placeholder | |
| 0x00000ce8 | ops_taps_fra_b1_sar_0to3 | placeholder | |
| 0x00000cec | ops_taps_fra_b1_sar_4to7 | placeholder | |
| 0x00000cf0 | ops_taps_fra_b1_sar_8to11 | placeholder | |
| 0x00000cf4 | ops_taps_fra_b1_sar_12to15 | placeholder | |
| 0x00000cf8 | ops_taps_fra_b1_sar_16to19 | placeholder | |
| 0x00000cfc | ops_taps_fra_b1_sar_20to23 | placeholder | |
| 0x00000d00 | ops_taps_fra_b1_sar_24to27 | placeholder | |
| 0x00000d04 | ops_taps_fra_b1_sar_28to31 | placeholder | |
| 0x00000d08 | ops_taps_fra_b1_sar_32to35 | placeholder | |
| 0x00000d0c | ops_taps_fra_b1_sar_36to39 | placeholder | |
| 0x00000d10 | ops_taps_fra_b1_sar_40to43 | placeholder | |
| 0x00000d14 | ops_taps_fra_b1_sar_44to47 | placeholder | |
| 0x00000d18 | ops_taps_fra_b1_sar_48to51 | placeholder | |
| 0x00000d1c | ops_taps_fra_b1_sar_52to55 | placeholder | |
| 0x00000d20 | ops_taps_fra_b1_sar_56to59 | placeholder | |
| 0x00000d24 | ops_taps_fra_b1_sar_60to63 | placeholder | |
| 0x00000d28 | ops_taps_fra_b2_sar_0to3 | placeholder | |
| 0x00000d2c | ops_taps_fra_b2_sar_4to7 | placeholder | |
| 0x00000d30 | ops_taps_fra_b2_sar_8to11 | placeholder | |
| 0x00000d34 | ops_taps_fra_b2_sar_12to15 | placeholder | |
| 0x00000d38 | ops_taps_fra_b2_sar_16to19 | placeholder | |
| 0x00000d3c | ops_taps_fra_b2_sar_20to23 | placeholder | |
| 0x00000d40 | ops_taps_fra_b2_sar_24to27 | placeholder | |
| 0x00000d44 | ops_taps_fra_b2_sar_28to31 | placeholder | |
| 0x00000d48 | ops_taps_fra_b2_sar_32to35 | placeholder | |
| 0x00000d4c | ops_taps_fra_b2_sar_36to39 | placeholder | |
| 0x00000d50 | ops_taps_fra_b2_sar_40to43 | placeholder | |
| 0x00000d54 | ops_taps_fra_b2_sar_44to47 | placeholder | |
| 0x00000d58 | ops_taps_fra_b2_sar_48to51 | placeholder | |
| 0x00000d5c | ops_taps_fra_b2_sar_52to55 | placeholder | |
| 0x00000d60 | ops_taps_fra_b2_sar_56to59 | placeholder | |
| 0x00000d64 | ops_taps_fra_b2_sar_60to63 | placeholder | |
| 0x00000d68 | ops_taps_fra_b3_sar_0to3 | placeholder | |
| 0x00000d6c | ops_taps_fra_b3_sar_4to7 | placeholder | |
| 0x00000d70 | ops_taps_fra_b3_sar_8to11 | placeholder | |
| 0x00000d74 | ops_taps_fra_b3_sar_12to15 | placeholder | |
| 0x00000d78 | ops_taps_fra_b3_sar_16to19 | placeholder | |
| 0x00000d7c | ops_taps_fra_b3_sar_20to23 | placeholder | |
| 0x00000d80 | ops_taps_fra_b3_sar_24to27 | placeholder | |
| 0x00000d84 | ops_taps_fra_b3_sar_28to31 | placeholder | |
| 0x00000d88 | ops_taps_fra_b3_sar_32to35 | placeholder | |
| 0x00000d8c | ops_taps_fra_b3_sar_36to39 | placeholder | |
| 0x00000d90 | ops_taps_fra_b3_sar_40to43 | placeholder | |
| 0x00000d94 | ops_taps_fra_b3_sar_44to47 | placeholder | |
| 0x00000d98 | ops_taps_fra_b3_sar_48to51 | placeholder | |
| 0x00000d9c | ops_taps_fra_b3_sar_52to55 | placeholder | |
| 0x00000da0 | ops_taps_fra_b3_sar_56to59 | placeholder | |
| 0x00000da4 | ops_taps_fra_b3_sar_60to63 | placeholder | |
| 0x00000da8 | ops_taps_fra_b4_sar_0to3 | placeholder | |
| 0x00000dac | ops_taps_fra_b4_sar_4to7 | placeholder | |
| 0x00000db0 | ops_taps_fra_b4_sar_8to11 | placeholder | |
| 0x00000db4 | ops_taps_fra_b4_sar_12to15 | placeholder | |
| 0x00000db8 | ops_taps_fra_b4_sar_16to19 | placeholder | |
| 0x00000dbc | ops_taps_fra_b4_sar_20to23 | placeholder | |
| 0x00000dc0 | ops_taps_fra_b4_sar_24to27 | placeholder | |
| 0x00000dc4 | ops_taps_fra_b4_sar_28to31 | placeholder | |
| 0x00000dc8 | ops_taps_fra_b4_sar_32to35 | placeholder | |
| 0x00000dcc | ops_taps_fra_b4_sar_36to39 | placeholder | |
| 0x00000dd0 | ops_taps_fra_b4_sar_40to43 | placeholder | |
| 0x00000dd4 | ops_taps_fra_b4_sar_44to47 | placeholder | |
| 0x00000dd8 | ops_taps_fra_b4_sar_48to51 | placeholder | |
| 0x00000ddc | ops_taps_fra_b4_sar_52to55 | placeholder | |
| 0x00000de0 | ops_taps_fra_b4_sar_56to59 | placeholder | |
| 0x00000de4 | ops_taps_fra_b4_sar_60to63 | placeholder | |
| 0x00000de8 | ops_taps_fra_b5_sar_0to3 | placeholder | |
| 0x00000dec | ops_taps_fra_b5_sar_4to7 | placeholder | |
| 0x00000df0 | ops_taps_fra_b5_sar_8to11 | placeholder | |
| 0x00000df4 | ops_taps_fra_b5_sar_12to15 | placeholder | |
| 0x00000df8 | ops_taps_fra_b5_sar_16to19 | placeholder | |
| 0x00000dfc | ops_taps_fra_b5_sar_20to23 | placeholder | |
| 0x00000e00 | ops_taps_fra_b5_sar_24to27 | placeholder | |
| 0x00000e04 | ops_taps_fra_b5_sar_28to31 | placeholder | |
| 0x00000e08 | ops_taps_fra_b5_sar_32to35 | placeholder | |
| 0x00000e0c | ops_taps_fra_b5_sar_36to39 | placeholder | |
| 0x00000e10 | ops_taps_fra_b5_sar_40to43 | placeholder | |
| 0x00000e14 | ops_taps_fra_b5_sar_44to47 | placeholder | |
| 0x00000e18 | ops_taps_fra_b5_sar_48to51 | placeholder | |
| 0x00000e1c | ops_taps_fra_b5_sar_52to55 | placeholder | |
| 0x00000e20 | ops_taps_fra_b5_sar_56to59 | placeholder | |
| 0x00000e24 | ops_taps_fra_b5_sar_60to63 | placeholder | |
| 0x00000e28 | ofc_control_4 | placeholder | |
| 0x00000e2c | ofc_control_5 | placeholder | |
| 0x00000e30 | ofc_control_6 | placeholder | |
| 0x00000e34 | ofc_control_7 | placeholder | |
| 0x00000e38 | cdr_ffe_ofc_control_4 | placeholder | |
| 0x00000e3c | cdr_ffe_ofc_control_5 | placeholder | |
| 0x00000e40 | cdr_ffe_ofc_control_6 | placeholder | |
| 0x00000e44 | cdr_ffe_ofc_control_7 | placeholder | |
| 0x00000e48 | adcofc_control_4 | placeholder | |
| 0x00000e4c | adcofc_control_5 | placeholder | |
| 0x00000e50 | adcofc_control_6 | placeholder | |
| 0x00000e54 | adcofc_control_7 | placeholder | |
| 0x00000e58 | 0x00000ef7 | (Not allocated) | |
| 0x00000ef8 | rx_sigdet_venv_ctrl1 | placeholder | |
| 0x00000efc | rx_sigdet_venv_ctrl2 | placeholder | |
| 0x00000f00 | rx_sigdet_venv_ctrl3 | placeholder | |
| 0x00000f04 | rx_sigdet_venv_status | placeholder | |
| 0x00000f08 | rx_sigdet_venv_status_clr | placeholder | |
| 0x00000f0c | 0x00000fd7 | (Not allocated) | |
| 0x00000fd8 | rxword_rw_spare_0 | Spare RW register | |
| 0x00000fdc | rxword_rw_spare_1 | Spare RW register | |
| 0x00000fe0 | rxword_rw_spare_2 | Spare RW register | |
| 0x00000fe4 | rxword_rw_spare_3 | Spare RW register | |
| 0x00000fe8 | rxword_ro_spare_0 | Spare RO register | |
| 0x00000fec | rxword_ro_spare_1 | Spare RO register |
Note: AddressOffsets before register name are offsets inside AddressMap (that is what the "+" means)
+0x00000000 Register(32 bit) ffe_coeff_set0_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e000 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x0000c0c0 | ||
| Undefined | 0x0000c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set0_coeff_post1 | ffe_coeff_set0_coeff_pre1 | - | ffe_coeff_set0_coeff_pre2 | - | ffe_coeff_set0_coeff_pre3 | ||||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set0_coeff_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set0_coeff_pre1 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set0_coeff_pre2 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set0_coeff_pre3 Reset: hex:0x00; |
+0x00000004 Register(32 bit) ffe_coeff_set0_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e004 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c000 | ||
| Undefined | 0xc0c0c000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set0_coeff_post5 | - | ffe_coeff_set0_coeff_post4 | - | ffe_coeff_set0_coeff_post3 | ffe_coeff_set0_coeff_post2 | |||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | RW/V | |||||||||||||||||||||||||
| [29:24] RW/V |
ffe_coeff_set0_coeff_post5 Reset: hex:0x00; |
| [21:16] RW/V |
ffe_coeff_set0_coeff_post4 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set0_coeff_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set0_coeff_post2 Reset: hex:0x00; |
+0x00000008 Register(32 bit) ffe_coeff_set0_2
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e008 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00c0c0c0 | ||
| Undefined | 0x00c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set0_coeff_post10 | ffe_coeff_set0_coeff_post9 | - | ffe_coeff_set0_coeff_post8 | - | ffe_coeff_set0_coeff_post7 | - | ffe_coeff_set0_coeff_post6 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set0_coeff_post10 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set0_coeff_post9 Reset: hex:0x0; |
| [21:16] RW/V |
ffe_coeff_set0_coeff_post8 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set0_coeff_post7 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set0_coeff_post6 Reset: hex:0x00; |
+0x0000000c Register(32 bit) ffe_coeff_set0_3
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e00c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set0_bankB_float3 | ffe_coeff_set0_bankB_float2 | ffe_coeff_set0_bankB_float1 | ffe_coeff_set0_bankA_float3 | ffe_coeff_set0_bankA_float2 | ffe_coeff_set0_bankA_float1 | ffe_coeff_set0_coeff_post12 | ffe_coeff_set0_coeff_post11 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set0_bankB_float3 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set0_bankB_float2 Reset: hex:0x0; |
| [23:20] RW/V |
ffe_coeff_set0_bankB_float1 Reset: hex:0x0; |
| [19:16] RW/V |
ffe_coeff_set0_bankA_float3 Reset: hex:0x0; |
| [15:12] RW/V |
ffe_coeff_set0_bankA_float2 Reset: hex:0x0; |
| [11:08] RW/V |
ffe_coeff_set0_bankA_float1 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set0_coeff_post12 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set0_coeff_post11 Reset: hex:0x0; |
+0x00000010 Register(32 bit) ffe_coeff_set0_4
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e010 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffff000 | ||
| Undefined | 0xfffff000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set0_bankC_float3 | ffe_coeff_set0_bankC_float2 | ffe_coeff_set0_bankC_float1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [11:08] RW/V |
ffe_coeff_set0_bankC_float3 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set0_bankC_float2 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set0_bankC_float1 Reset: hex:0x0; |
+0x00000014 Register(32 bit) ffe_coeff_set1_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e014 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x0000c0c0 | ||
| Undefined | 0x0000c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set1_coeff_post1 | ffe_coeff_set1_coeff_pre1 | - | ffe_coeff_set1_coeff_pre2 | - | ffe_coeff_set1_coeff_pre3 | ||||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set1_coeff_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set1_coeff_pre1 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set1_coeff_pre2 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set1_coeff_pre3 Reset: hex:0x00; |
+0x00000018 Register(32 bit) ffe_coeff_set1_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e018 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c000 | ||
| Undefined | 0xc0c0c000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set1_coeff_post5 | - | ffe_coeff_set1_coeff_post4 | - | ffe_coeff_set1_coeff_post3 | ffe_coeff_set1_coeff_post2 | |||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | RW/V | |||||||||||||||||||||||||
| [29:24] RW/V |
ffe_coeff_set1_coeff_post5 Reset: hex:0x00; |
| [21:16] RW/V |
ffe_coeff_set1_coeff_post4 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set1_coeff_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set1_coeff_post2 Reset: hex:0x00; |
+0x0000001c Register(32 bit) ffe_coeff_set1_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e01c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00c0c0c0 | ||
| Undefined | 0x00c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set1_coeff_post10 | ffe_coeff_set1_coeff_post9 | - | ffe_coeff_set1_coeff_post8 | - | ffe_coeff_set1_coeff_post7 | - | ffe_coeff_set1_coeff_post6 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set1_coeff_post10 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set1_coeff_post9 Reset: hex:0x0; |
| [21:16] RW/V |
ffe_coeff_set1_coeff_post8 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set1_coeff_post7 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set1_coeff_post6 Reset: hex:0x00; |
+0x00000020 Register(32 bit) ffe_coeff_set1_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e020 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set1_bankB_float3 | ffe_coeff_set1_bankB_float2 | ffe_coeff_set1_bankB_float1 | ffe_coeff_set1_bankA_float3 | ffe_coeff_set1_bankA_float2 | ffe_coeff_set1_bankA_float1 | ffe_coeff_set1_coeff_post12 | ffe_coeff_set1_coeff_post11 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set1_bankB_float3 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set1_bankB_float2 Reset: hex:0x0; |
| [23:20] RW/V |
ffe_coeff_set1_bankB_float1 Reset: hex:0x0; |
| [19:16] RW/V |
ffe_coeff_set1_bankA_float3 Reset: hex:0x0; |
| [15:12] RW/V |
ffe_coeff_set1_bankA_float2 Reset: hex:0x0; |
| [11:08] RW/V |
ffe_coeff_set1_bankA_float1 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set1_coeff_post12 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set1_coeff_post11 Reset: hex:0x0; |
+0x00000024 Register(32 bit) ffe_coeff_set1_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e024 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffff000 | ||
| Undefined | 0xfffff000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set1_bankC_float3 | ffe_coeff_set1_bankC_float2 | ffe_coeff_set1_bankC_float1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [11:08] RW/V |
ffe_coeff_set1_bankC_float3 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set1_bankC_float2 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set1_bankC_float1 Reset: hex:0x0; |
+0x00000028 Register(32 bit) ffe_coeff_set2_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e028 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x0000c0c0 | ||
| Undefined | 0x0000c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set2_coeff_post1 | ffe_coeff_set2_coeff_pre1 | - | ffe_coeff_set2_coeff_pre2 | - | ffe_coeff_set2_coeff_pre3 | ||||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set2_coeff_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set2_coeff_pre1 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set2_coeff_pre2 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set2_coeff_pre3 Reset: hex:0x00; |
+0x0000002c Register(32 bit) ffe_coeff_set2_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e02c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c000 | ||
| Undefined | 0xc0c0c000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set2_coeff_post5 | - | ffe_coeff_set2_coeff_post4 | - | ffe_coeff_set2_coeff_post3 | ffe_coeff_set2_coeff_post2 | |||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | RW/V | |||||||||||||||||||||||||
| [29:24] RW/V |
ffe_coeff_set2_coeff_post5 Reset: hex:0x00; |
| [21:16] RW/V |
ffe_coeff_set2_coeff_post4 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set2_coeff_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set2_coeff_post2 Reset: hex:0x00; |
+0x00000030 Register(32 bit) ffe_coeff_set2_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e030 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00c0c0c0 | ||
| Undefined | 0x00c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set2_coeff_post10 | ffe_coeff_set2_coeff_post9 | - | ffe_coeff_set2_coeff_post8 | - | ffe_coeff_set2_coeff_post7 | - | ffe_coeff_set2_coeff_post6 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set2_coeff_post10 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set2_coeff_post9 Reset: hex:0x0; |
| [21:16] RW/V |
ffe_coeff_set2_coeff_post8 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set2_coeff_post7 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set2_coeff_post6 Reset: hex:0x00; |
+0x00000034 Register(32 bit) ffe_coeff_set2_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e034 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set2_bankB_float3 | ffe_coeff_set2_bankB_float2 | ffe_coeff_set2_bankB_float1 | ffe_coeff_set2_bankA_float3 | ffe_coeff_set2_bankA_float2 | ffe_coeff_set2_bankA_float1 | ffe_coeff_set2_coeff_post12 | ffe_coeff_set2_coeff_post11 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set2_bankB_float3 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set2_bankB_float2 Reset: hex:0x0; |
| [23:20] RW/V |
ffe_coeff_set2_bankB_float1 Reset: hex:0x0; |
| [19:16] RW/V |
ffe_coeff_set2_bankA_float3 Reset: hex:0x0; |
| [15:12] RW/V |
ffe_coeff_set2_bankA_float2 Reset: hex:0x0; |
| [11:08] RW/V |
ffe_coeff_set2_bankA_float1 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set2_coeff_post12 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set2_coeff_post11 Reset: hex:0x0; |
+0x00000038 Register(32 bit) ffe_coeff_set2_4
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e038 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffff000 | ||
| Undefined | 0xfffff000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set2_bankC_float3 | ffe_coeff_set2_bankC_float2 | ffe_coeff_set2_bankC_float1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [11:08] RW/V |
ffe_coeff_set2_bankC_float3 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set2_bankC_float2 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set2_bankC_float1 Reset: hex:0x0; |
+0x0000003c Register(32 bit) ffe_coeff_set3_0
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e03c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x0000c0c0 | ||
| Undefined | 0x0000c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set3_coeff_post1 | ffe_coeff_set3_coeff_pre1 | - | ffe_coeff_set3_coeff_pre2 | - | ffe_coeff_set3_coeff_pre3 | ||||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set3_coeff_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set3_coeff_pre1 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set3_coeff_pre2 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set3_coeff_pre3 Reset: hex:0x00; |
+0x00000040 Register(32 bit) ffe_coeff_set3_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e040 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c000 | ||
| Undefined | 0xc0c0c000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set3_coeff_post5 | - | ffe_coeff_set3_coeff_post4 | - | ffe_coeff_set3_coeff_post3 | ffe_coeff_set3_coeff_post2 | |||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | RW/V | |||||||||||||||||||||||||
| [29:24] RW/V |
ffe_coeff_set3_coeff_post5 Reset: hex:0x00; |
| [21:16] RW/V |
ffe_coeff_set3_coeff_post4 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set3_coeff_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set3_coeff_post2 Reset: hex:0x00; |
+0x00000044 Register(32 bit) ffe_coeff_set3_2
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e044 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00c0c0c0 | ||
| Undefined | 0x00c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set3_coeff_post10 | ffe_coeff_set3_coeff_post9 | - | ffe_coeff_set3_coeff_post8 | - | ffe_coeff_set3_coeff_post7 | - | ffe_coeff_set3_coeff_post6 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set3_coeff_post10 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set3_coeff_post9 Reset: hex:0x0; |
| [21:16] RW/V |
ffe_coeff_set3_coeff_post8 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set3_coeff_post7 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set3_coeff_post6 Reset: hex:0x00; |
+0x00000048 Register(32 bit) ffe_coeff_set3_3
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e048 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set3_bankB_float3 | ffe_coeff_set3_bankB_float2 | ffe_coeff_set3_bankB_float1 | ffe_coeff_set3_bankA_float3 | ffe_coeff_set3_bankA_float2 | ffe_coeff_set3_bankA_float1 | ffe_coeff_set3_coeff_post12 | ffe_coeff_set3_coeff_post11 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set3_bankB_float3 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set3_bankB_float2 Reset: hex:0x0; |
| [23:20] RW/V |
ffe_coeff_set3_bankB_float1 Reset: hex:0x0; |
| [19:16] RW/V |
ffe_coeff_set3_bankA_float3 Reset: hex:0x0; |
| [15:12] RW/V |
ffe_coeff_set3_bankA_float2 Reset: hex:0x0; |
| [11:08] RW/V |
ffe_coeff_set3_bankA_float1 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set3_coeff_post12 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set3_coeff_post11 Reset: hex:0x0; |
+0x0000004c Register(32 bit) ffe_coeff_set3_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e04c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffff000 | ||
| Undefined | 0xfffff000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set3_bankC_float3 | ffe_coeff_set3_bankC_float2 | ffe_coeff_set3_bankC_float1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [11:08] RW/V |
ffe_coeff_set3_bankC_float3 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set3_bankC_float2 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set3_bankC_float1 Reset: hex:0x0; |
+0x00000050 Register(32 bit) ffe_coeff_set4_0
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e050 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x0000c0c0 | ||
| Undefined | 0x0000c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set4_coeff_post1 | ffe_coeff_set4_coeff_pre1 | - | ffe_coeff_set4_coeff_pre2 | - | ffe_coeff_set4_coeff_pre3 | ||||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set4_coeff_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set4_coeff_pre1 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set4_coeff_pre2 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set4_coeff_pre3 Reset: hex:0x00; |
+0x00000054 Register(32 bit) ffe_coeff_set4_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e054 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c000 | ||
| Undefined | 0xc0c0c000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set4_coeff_post5 | - | ffe_coeff_set4_coeff_post4 | - | ffe_coeff_set4_coeff_post3 | ffe_coeff_set4_coeff_post2 | |||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | RW/V | |||||||||||||||||||||||||
| [29:24] RW/V |
ffe_coeff_set4_coeff_post5 Reset: hex:0x00; |
| [21:16] RW/V |
ffe_coeff_set4_coeff_post4 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set4_coeff_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set4_coeff_post2 Reset: hex:0x00; |
+0x00000058 Register(32 bit) ffe_coeff_set4_2
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e058 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00c0c0c0 | ||
| Undefined | 0x00c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set4_coeff_post10 | ffe_coeff_set4_coeff_post9 | - | ffe_coeff_set4_coeff_post8 | - | ffe_coeff_set4_coeff_post7 | - | ffe_coeff_set4_coeff_post6 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set4_coeff_post10 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set4_coeff_post9 Reset: hex:0x0; |
| [21:16] RW/V |
ffe_coeff_set4_coeff_post8 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set4_coeff_post7 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set4_coeff_post6 Reset: hex:0x00; |
+0x0000005c Register(32 bit) ffe_coeff_set4_3
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e05c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set4_bankB_float3 | ffe_coeff_set4_bankB_float2 | ffe_coeff_set4_bankB_float1 | ffe_coeff_set4_bankA_float3 | ffe_coeff_set4_bankA_float2 | ffe_coeff_set4_bankA_float1 | ffe_coeff_set4_coeff_post12 | ffe_coeff_set4_coeff_post11 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set4_bankB_float3 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set4_bankB_float2 Reset: hex:0x0; |
| [23:20] RW/V |
ffe_coeff_set4_bankB_float1 Reset: hex:0x0; |
| [19:16] RW/V |
ffe_coeff_set4_bankA_float3 Reset: hex:0x0; |
| [15:12] RW/V |
ffe_coeff_set4_bankA_float2 Reset: hex:0x0; |
| [11:08] RW/V |
ffe_coeff_set4_bankA_float1 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set4_coeff_post12 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set4_coeff_post11 Reset: hex:0x0; |
+0x00000060 Register(32 bit) ffe_coeff_set4_4
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e060 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffff000 | ||
| Undefined | 0xfffff000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set4_bankC_float3 | ffe_coeff_set4_bankC_float2 | ffe_coeff_set4_bankC_float1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [11:08] RW/V |
ffe_coeff_set4_bankC_float3 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set4_bankC_float2 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set4_bankC_float1 Reset: hex:0x0; |
+0x00000064 Register(32 bit) ffe_coeff_set5_0
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e064 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x0000c0c0 | ||
| Undefined | 0x0000c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set5_coeff_post1 | ffe_coeff_set5_coeff_pre1 | - | ffe_coeff_set5_coeff_pre2 | - | ffe_coeff_set5_coeff_pre3 | ||||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set5_coeff_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set5_coeff_pre1 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set5_coeff_pre2 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set5_coeff_pre3 Reset: hex:0x00; |
+0x00000068 Register(32 bit) ffe_coeff_set5_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e068 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c000 | ||
| Undefined | 0xc0c0c000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set5_coeff_post5 | - | ffe_coeff_set5_coeff_post4 | - | ffe_coeff_set5_coeff_post3 | ffe_coeff_set5_coeff_post2 | |||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | RW/V | |||||||||||||||||||||||||
| [29:24] RW/V |
ffe_coeff_set5_coeff_post5 Reset: hex:0x00; |
| [21:16] RW/V |
ffe_coeff_set5_coeff_post4 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set5_coeff_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set5_coeff_post2 Reset: hex:0x00; |
+0x0000006c Register(32 bit) ffe_coeff_set5_2
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e06c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00c0c0c0 | ||
| Undefined | 0x00c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set5_coeff_post10 | ffe_coeff_set5_coeff_post9 | - | ffe_coeff_set5_coeff_post8 | - | ffe_coeff_set5_coeff_post7 | - | ffe_coeff_set5_coeff_post6 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set5_coeff_post10 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set5_coeff_post9 Reset: hex:0x0; |
| [21:16] RW/V |
ffe_coeff_set5_coeff_post8 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set5_coeff_post7 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set5_coeff_post6 Reset: hex:0x00; |
+0x00000070 Register(32 bit) ffe_coeff_set5_3
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e070 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set5_bankB_float3 | ffe_coeff_set5_bankB_float2 | ffe_coeff_set5_bankB_float1 | ffe_coeff_set5_bankA_float3 | ffe_coeff_set5_bankA_float2 | ffe_coeff_set5_bankA_float1 | ffe_coeff_set5_coeff_post12 | ffe_coeff_set5_coeff_post11 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set5_bankB_float3 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set5_bankB_float2 Reset: hex:0x0; |
| [23:20] RW/V |
ffe_coeff_set5_bankB_float1 Reset: hex:0x0; |
| [19:16] RW/V |
ffe_coeff_set5_bankA_float3 Reset: hex:0x0; |
| [15:12] RW/V |
ffe_coeff_set5_bankA_float2 Reset: hex:0x0; |
| [11:08] RW/V |
ffe_coeff_set5_bankA_float1 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set5_coeff_post12 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set5_coeff_post11 Reset: hex:0x0; |
+0x00000074 Register(32 bit) ffe_coeff_set5_4
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e074 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffff000 | ||
| Undefined | 0xfffff000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set5_bankC_float3 | ffe_coeff_set5_bankC_float2 | ffe_coeff_set5_bankC_float1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [11:08] RW/V |
ffe_coeff_set5_bankC_float3 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set5_bankC_float2 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set5_bankC_float1 Reset: hex:0x0; |
+0x00000078 Register(32 bit) ffe_coeff_set6_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e078 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x0000c0c0 | ||
| Undefined | 0x0000c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set6_coeff_post1 | ffe_coeff_set6_coeff_pre1 | - | ffe_coeff_set6_coeff_pre2 | - | ffe_coeff_set6_coeff_pre3 | ||||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set6_coeff_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set6_coeff_pre1 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set6_coeff_pre2 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set6_coeff_pre3 Reset: hex:0x00; |
+0x0000007c Register(32 bit) ffe_coeff_set6_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e07c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c000 | ||
| Undefined | 0xc0c0c000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set6_coeff_post5 | - | ffe_coeff_set6_coeff_post4 | - | ffe_coeff_set6_coeff_post3 | ffe_coeff_set6_coeff_post2 | |||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | RW/V | |||||||||||||||||||||||||
| [29:24] RW/V |
ffe_coeff_set6_coeff_post5 Reset: hex:0x00; |
| [21:16] RW/V |
ffe_coeff_set6_coeff_post4 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set6_coeff_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set6_coeff_post2 Reset: hex:0x00; |
+0x00000080 Register(32 bit) ffe_coeff_set6_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e080 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00c0c0c0 | ||
| Undefined | 0x00c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set6_coeff_post10 | ffe_coeff_set6_coeff_post9 | - | ffe_coeff_set6_coeff_post8 | - | ffe_coeff_set6_coeff_post7 | - | ffe_coeff_set6_coeff_post6 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set6_coeff_post10 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set6_coeff_post9 Reset: hex:0x0; |
| [21:16] RW/V |
ffe_coeff_set6_coeff_post8 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set6_coeff_post7 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set6_coeff_post6 Reset: hex:0x00; |
+0x00000084 Register(32 bit) ffe_coeff_set6_3
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e084 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set6_bankB_float3 | ffe_coeff_set6_bankB_float2 | ffe_coeff_set6_bankB_float1 | ffe_coeff_set6_bankA_float3 | ffe_coeff_set6_bankA_float2 | ffe_coeff_set6_bankA_float1 | ffe_coeff_set6_coeff_post12 | ffe_coeff_set6_coeff_post11 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set6_bankB_float3 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set6_bankB_float2 Reset: hex:0x0; |
| [23:20] RW/V |
ffe_coeff_set6_bankB_float1 Reset: hex:0x0; |
| [19:16] RW/V |
ffe_coeff_set6_bankA_float3 Reset: hex:0x0; |
| [15:12] RW/V |
ffe_coeff_set6_bankA_float2 Reset: hex:0x0; |
| [11:08] RW/V |
ffe_coeff_set6_bankA_float1 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set6_coeff_post12 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set6_coeff_post11 Reset: hex:0x0; |
+0x00000088 Register(32 bit) ffe_coeff_set6_4
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e088 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffff000 | ||
| Undefined | 0xfffff000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set6_bankC_float3 | ffe_coeff_set6_bankC_float2 | ffe_coeff_set6_bankC_float1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [11:08] RW/V |
ffe_coeff_set6_bankC_float3 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set6_bankC_float2 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set6_bankC_float1 Reset: hex:0x0; |
+0x0000008c Register(32 bit) ffe_coeff_set7_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e08c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x0000c0c0 | ||
| Undefined | 0x0000c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set7_coeff_post1 | ffe_coeff_set7_coeff_pre1 | - | ffe_coeff_set7_coeff_pre2 | - | ffe_coeff_set7_coeff_pre3 | ||||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set7_coeff_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set7_coeff_pre1 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set7_coeff_pre2 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set7_coeff_pre3 Reset: hex:0x00; |
+0x00000090 Register(32 bit) ffe_coeff_set7_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e090 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c000 | ||
| Undefined | 0xc0c0c000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set7_coeff_post5 | - | ffe_coeff_set7_coeff_post4 | - | ffe_coeff_set7_coeff_post3 | ffe_coeff_set7_coeff_post2 | |||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | RW/V | |||||||||||||||||||||||||
| [29:24] RW/V |
ffe_coeff_set7_coeff_post5 Reset: hex:0x00; |
| [21:16] RW/V |
ffe_coeff_set7_coeff_post4 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set7_coeff_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set7_coeff_post2 Reset: hex:0x00; |
+0x00000094 Register(32 bit) ffe_coeff_set7_2
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e094 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00c0c0c0 | ||
| Undefined | 0x00c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set7_coeff_post10 | ffe_coeff_set7_coeff_post9 | - | ffe_coeff_set7_coeff_post8 | - | ffe_coeff_set7_coeff_post7 | - | ffe_coeff_set7_coeff_post6 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set7_coeff_post10 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set7_coeff_post9 Reset: hex:0x0; |
| [21:16] RW/V |
ffe_coeff_set7_coeff_post8 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set7_coeff_post7 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set7_coeff_post6 Reset: hex:0x00; |
+0x00000098 Register(32 bit) ffe_coeff_set7_3
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e098 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set7_bankB_float3 | ffe_coeff_set7_bankB_float2 | ffe_coeff_set7_bankB_float1 | ffe_coeff_set7_bankA_float3 | ffe_coeff_set7_bankA_float2 | ffe_coeff_set7_bankA_float1 | ffe_coeff_set7_coeff_post12 | ffe_coeff_set7_coeff_post11 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set7_bankB_float3 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set7_bankB_float2 Reset: hex:0x0; |
| [23:20] RW/V |
ffe_coeff_set7_bankB_float1 Reset: hex:0x0; |
| [19:16] RW/V |
ffe_coeff_set7_bankA_float3 Reset: hex:0x0; |
| [15:12] RW/V |
ffe_coeff_set7_bankA_float2 Reset: hex:0x0; |
| [11:08] RW/V |
ffe_coeff_set7_bankA_float1 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set7_coeff_post12 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set7_coeff_post11 Reset: hex:0x0; |
+0x0000009c Register(32 bit) ffe_coeff_set7_4
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e09c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffff000 | ||
| Undefined | 0xfffff000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set7_bankC_float3 | ffe_coeff_set7_bankC_float2 | ffe_coeff_set7_bankC_float1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [11:08] RW/V |
ffe_coeff_set7_bankC_float3 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set7_bankC_float2 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set7_bankC_float1 Reset: hex:0x0; |
+0x000000a0 Register(32 bit) ffe_coeff_set8_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0a0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x0000c0c0 | ||
| Undefined | 0x0000c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set8_coeff_post1 | ffe_coeff_set8_coeff_pre1 | - | ffe_coeff_set8_coeff_pre2 | - | ffe_coeff_set8_coeff_pre3 | ||||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set8_coeff_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set8_coeff_pre1 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set8_coeff_pre2 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set8_coeff_pre3 Reset: hex:0x00; |
+0x000000a4 Register(32 bit) ffe_coeff_set8_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0a4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c000 | ||
| Undefined | 0xc0c0c000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set8_coeff_post5 | - | ffe_coeff_set8_coeff_post4 | - | ffe_coeff_set8_coeff_post3 | ffe_coeff_set8_coeff_post2 | |||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | RW/V | |||||||||||||||||||||||||
| [29:24] RW/V |
ffe_coeff_set8_coeff_post5 Reset: hex:0x00; |
| [21:16] RW/V |
ffe_coeff_set8_coeff_post4 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set8_coeff_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set8_coeff_post2 Reset: hex:0x00; |
+0x000000a8 Register(32 bit) ffe_coeff_set8_2
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0a8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00c0c0c0 | ||
| Undefined | 0x00c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set8_coeff_post10 | ffe_coeff_set8_coeff_post9 | - | ffe_coeff_set8_coeff_post8 | - | ffe_coeff_set8_coeff_post7 | - | ffe_coeff_set8_coeff_post6 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set8_coeff_post10 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set8_coeff_post9 Reset: hex:0x0; |
| [21:16] RW/V |
ffe_coeff_set8_coeff_post8 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set8_coeff_post7 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set8_coeff_post6 Reset: hex:0x00; |
+0x000000ac Register(32 bit) ffe_coeff_set8_3
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0ac at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set8_bankB_float3 | ffe_coeff_set8_bankB_float2 | ffe_coeff_set8_bankB_float1 | ffe_coeff_set8_bankA_float3 | ffe_coeff_set8_bankA_float2 | ffe_coeff_set8_bankA_float1 | ffe_coeff_set8_coeff_post12 | ffe_coeff_set8_coeff_post11 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set8_bankB_float3 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set8_bankB_float2 Reset: hex:0x0; |
| [23:20] RW/V |
ffe_coeff_set8_bankB_float1 Reset: hex:0x0; |
| [19:16] RW/V |
ffe_coeff_set8_bankA_float3 Reset: hex:0x0; |
| [15:12] RW/V |
ffe_coeff_set8_bankA_float2 Reset: hex:0x0; |
| [11:08] RW/V |
ffe_coeff_set8_bankA_float1 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set8_coeff_post12 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set8_coeff_post11 Reset: hex:0x0; |
+0x000000b0 Register(32 bit) ffe_coeff_set8_4
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0b0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffff000 | ||
| Undefined | 0xfffff000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set8_bankC_float3 | ffe_coeff_set8_bankC_float2 | ffe_coeff_set8_bankC_float1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [11:08] RW/V |
ffe_coeff_set8_bankC_float3 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set8_bankC_float2 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set8_bankC_float1 Reset: hex:0x0; |
+0x000000b4 Register(32 bit) ffe_coeff_set9_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0b4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x0000c0c0 | ||
| Undefined | 0x0000c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set9_coeff_post1 | ffe_coeff_set9_coeff_pre1 | - | ffe_coeff_set9_coeff_pre2 | - | ffe_coeff_set9_coeff_pre3 | ||||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set9_coeff_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set9_coeff_pre1 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set9_coeff_pre2 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set9_coeff_pre3 Reset: hex:0x00; |
+0x000000b8 Register(32 bit) ffe_coeff_set9_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0b8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c000 | ||
| Undefined | 0xc0c0c000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set9_coeff_post5 | - | ffe_coeff_set9_coeff_post4 | - | ffe_coeff_set9_coeff_post3 | ffe_coeff_set9_coeff_post2 | |||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | RW/V | |||||||||||||||||||||||||
| [29:24] RW/V |
ffe_coeff_set9_coeff_post5 Reset: hex:0x00; |
| [21:16] RW/V |
ffe_coeff_set9_coeff_post4 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set9_coeff_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set9_coeff_post2 Reset: hex:0x00; |
+0x000000bc Register(32 bit) ffe_coeff_set9_2
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0bc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00c0c0c0 | ||
| Undefined | 0x00c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set9_coeff_post10 | ffe_coeff_set9_coeff_post9 | - | ffe_coeff_set9_coeff_post8 | - | ffe_coeff_set9_coeff_post7 | - | ffe_coeff_set9_coeff_post6 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set9_coeff_post10 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set9_coeff_post9 Reset: hex:0x0; |
| [21:16] RW/V |
ffe_coeff_set9_coeff_post8 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set9_coeff_post7 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set9_coeff_post6 Reset: hex:0x00; |
+0x000000c0 Register(32 bit) ffe_coeff_set9_3
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0c0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set9_bankB_float3 | ffe_coeff_set9_bankB_float2 | ffe_coeff_set9_bankB_float1 | ffe_coeff_set9_bankA_float3 | ffe_coeff_set9_bankA_float2 | ffe_coeff_set9_bankA_float1 | ffe_coeff_set9_coeff_post12 | ffe_coeff_set9_coeff_post11 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set9_bankB_float3 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set9_bankB_float2 Reset: hex:0x0; |
| [23:20] RW/V |
ffe_coeff_set9_bankB_float1 Reset: hex:0x0; |
| [19:16] RW/V |
ffe_coeff_set9_bankA_float3 Reset: hex:0x0; |
| [15:12] RW/V |
ffe_coeff_set9_bankA_float2 Reset: hex:0x0; |
| [11:08] RW/V |
ffe_coeff_set9_bankA_float1 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set9_coeff_post12 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set9_coeff_post11 Reset: hex:0x0; |
+0x000000c4 Register(32 bit) ffe_coeff_set9_4
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0c4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffff000 | ||
| Undefined | 0xfffff000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set9_bankC_float3 | ffe_coeff_set9_bankC_float2 | ffe_coeff_set9_bankC_float1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [11:08] RW/V |
ffe_coeff_set9_bankC_float3 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set9_bankC_float2 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set9_bankC_float1 Reset: hex:0x0; |
+0x000000cc Register(32 bit) ffe_coeff_set10_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0cc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x0000c0c0 | ||
| Undefined | 0x0000c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set10_coeff_post1 | ffe_coeff_set10_coeff_pre1 | - | ffe_coeff_set10_coeff_pre2 | - | ffe_coeff_set10_coeff_pre3 | ||||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set10_coeff_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set10_coeff_pre1 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set10_coeff_pre2 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set10_coeff_pre3 Reset: hex:0x00; |
+0x000000d0 Register(32 bit) ffe_coeff_set10_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0d0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c000 | ||
| Undefined | 0xc0c0c000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set10_coeff_post5 | - | ffe_coeff_set10_coeff_post4 | - | ffe_coeff_set10_coeff_post3 | ffe_coeff_set10_coeff_post2 | |||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | RW/V | |||||||||||||||||||||||||
| [29:24] RW/V |
ffe_coeff_set10_coeff_post5 Reset: hex:0x00; |
| [21:16] RW/V |
ffe_coeff_set10_coeff_post4 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set10_coeff_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set10_coeff_post2 Reset: hex:0x00; |
+0x000000d4 Register(32 bit) ffe_coeff_set10_2
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0d4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00c0c0c0 | ||
| Undefined | 0x00c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set10_coeff_post10 | ffe_coeff_set10_coeff_post9 | - | ffe_coeff_set10_coeff_post8 | - | ffe_coeff_set10_coeff_post7 | - | ffe_coeff_set10_coeff_post6 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set10_coeff_post10 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set10_coeff_post9 Reset: hex:0x0; |
| [21:16] RW/V |
ffe_coeff_set10_coeff_post8 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set10_coeff_post7 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set10_coeff_post6 Reset: hex:0x00; |
+0x000000d8 Register(32 bit) ffe_coeff_set10_3
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0d8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set10_bankB_float3 | ffe_coeff_set10_bankB_float2 | ffe_coeff_set10_bankB_float1 | ffe_coeff_set10_bankA_float3 | ffe_coeff_set10_bankA_float2 | ffe_coeff_set10_bankA_float1 | ffe_coeff_set10_coeff_post12 | ffe_coeff_set10_coeff_post11 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set10_bankB_float3 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set10_bankB_float2 Reset: hex:0x0; |
| [23:20] RW/V |
ffe_coeff_set10_bankB_float1 Reset: hex:0x0; |
| [19:16] RW/V |
ffe_coeff_set10_bankA_float3 Reset: hex:0x0; |
| [15:12] RW/V |
ffe_coeff_set10_bankA_float2 Reset: hex:0x0; |
| [11:08] RW/V |
ffe_coeff_set10_bankA_float1 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set10_coeff_post12 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set10_coeff_post11 Reset: hex:0x0; |
+0x000000dc Register(32 bit) ffe_coeff_set10_4
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0dc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffff000 | ||
| Undefined | 0xfffff000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set10_bankC_float3 | ffe_coeff_set10_bankC_float2 | ffe_coeff_set10_bankC_float1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [11:08] RW/V |
ffe_coeff_set10_bankC_float3 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set10_bankC_float2 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set10_bankC_float1 Reset: hex:0x0; |
+0x000000e0 Register(32 bit) ffe_coeff_set11_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0e0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x0000c0c0 | ||
| Undefined | 0x0000c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set11_coeff_post1 | ffe_coeff_set11_coeff_pre1 | - | ffe_coeff_set11_coeff_pre2 | - | ffe_coeff_set11_coeff_pre3 | ||||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set11_coeff_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set11_coeff_pre1 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set11_coeff_pre2 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set11_coeff_pre3 Reset: hex:0x00; |
+0x000000e4 Register(32 bit) ffe_coeff_set11_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0e4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c000 | ||
| Undefined | 0xc0c0c000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set11_coeff_post5 | - | ffe_coeff_set11_coeff_post4 | - | ffe_coeff_set11_coeff_post3 | ffe_coeff_set11_coeff_post2 | |||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | RW/V | |||||||||||||||||||||||||
| [29:24] RW/V |
ffe_coeff_set11_coeff_post5 Reset: hex:0x00; |
| [21:16] RW/V |
ffe_coeff_set11_coeff_post4 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set11_coeff_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set11_coeff_post2 Reset: hex:0x00; |
+0x000000e8 Register(32 bit) ffe_coeff_set11_2
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0e8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00c0c0c0 | ||
| Undefined | 0x00c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set11_coeff_post10 | ffe_coeff_set11_coeff_post9 | - | ffe_coeff_set11_coeff_post8 | - | ffe_coeff_set11_coeff_post7 | - | ffe_coeff_set11_coeff_post6 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set11_coeff_post10 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set11_coeff_post9 Reset: hex:0x0; |
| [21:16] RW/V |
ffe_coeff_set11_coeff_post8 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set11_coeff_post7 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set11_coeff_post6 Reset: hex:0x00; |
+0x000000ec Register(32 bit) ffe_coeff_set11_3
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0ec at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set11_bankB_float3 | ffe_coeff_set11_bankB_float2 | ffe_coeff_set11_bankB_float1 | ffe_coeff_set11_bankA_float3 | ffe_coeff_set11_bankA_float2 | ffe_coeff_set11_bankA_float1 | ffe_coeff_set11_coeff_post12 | ffe_coeff_set11_coeff_post11 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set11_bankB_float3 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set11_bankB_float2 Reset: hex:0x0; |
| [23:20] RW/V |
ffe_coeff_set11_bankB_float1 Reset: hex:0x0; |
| [19:16] RW/V |
ffe_coeff_set11_bankA_float3 Reset: hex:0x0; |
| [15:12] RW/V |
ffe_coeff_set11_bankA_float2 Reset: hex:0x0; |
| [11:08] RW/V |
ffe_coeff_set11_bankA_float1 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set11_coeff_post12 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set11_coeff_post11 Reset: hex:0x0; |
+0x000000f0 Register(32 bit) ffe_coeff_set11_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0f0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffff000 | ||
| Undefined | 0xfffff000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set11_bankC_float3 | ffe_coeff_set11_bankC_float2 | ffe_coeff_set11_bankC_float1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [11:08] RW/V |
ffe_coeff_set11_bankC_float3 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set11_bankC_float2 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set11_bankC_float1 Reset: hex:0x0; |
+0x000000f4 Register(32 bit) ffe_coeff_set12_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0f4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x0000c0c0 | ||
| Undefined | 0x0000c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set12_coeff_post1 | ffe_coeff_set12_coeff_pre1 | - | ffe_coeff_set12_coeff_pre2 | - | ffe_coeff_set12_coeff_pre3 | ||||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set12_coeff_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set12_coeff_pre1 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set12_coeff_pre2 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set12_coeff_pre3 Reset: hex:0x00; |
+0x000000f8 Register(32 bit) ffe_coeff_set12_1
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0f8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c000 | ||
| Undefined | 0xc0c0c000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set12_coeff_post5 | - | ffe_coeff_set12_coeff_post4 | - | ffe_coeff_set12_coeff_post3 | ffe_coeff_set12_coeff_post2 | |||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | RW/V | |||||||||||||||||||||||||
| [29:24] RW/V |
ffe_coeff_set12_coeff_post5 Reset: hex:0x00; |
| [21:16] RW/V |
ffe_coeff_set12_coeff_post4 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set12_coeff_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set12_coeff_post2 Reset: hex:0x00; |
+0x000000fc Register(32 bit) ffe_coeff_set12_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e0fc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00c0c0c0 | ||
| Undefined | 0x00c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set12_coeff_post10 | ffe_coeff_set12_coeff_post9 | - | ffe_coeff_set12_coeff_post8 | - | ffe_coeff_set12_coeff_post7 | - | ffe_coeff_set12_coeff_post6 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set12_coeff_post10 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set12_coeff_post9 Reset: hex:0x0; |
| [21:16] RW/V |
ffe_coeff_set12_coeff_post8 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set12_coeff_post7 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set12_coeff_post6 Reset: hex:0x00; |
+0x00000100 Register(32 bit) ffe_coeff_set12_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e100 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set12_bankB_float3 | ffe_coeff_set12_bankB_float2 | ffe_coeff_set12_bankB_float1 | ffe_coeff_set12_bankA_float3 | ffe_coeff_set12_bankA_float2 | ffe_coeff_set12_bankA_float1 | ffe_coeff_set12_coeff_post12 | ffe_coeff_set12_coeff_post11 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set12_bankB_float3 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set12_bankB_float2 Reset: hex:0x0; |
| [23:20] RW/V |
ffe_coeff_set12_bankB_float1 Reset: hex:0x0; |
| [19:16] RW/V |
ffe_coeff_set12_bankA_float3 Reset: hex:0x0; |
| [15:12] RW/V |
ffe_coeff_set12_bankA_float2 Reset: hex:0x0; |
| [11:08] RW/V |
ffe_coeff_set12_bankA_float1 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set12_coeff_post12 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set12_coeff_post11 Reset: hex:0x0; |
+0x00000104 Register(32 bit) ffe_coeff_set12_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e104 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffff000 | ||
| Undefined | 0xfffff000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set12_bankC_float3 | ffe_coeff_set12_bankC_float2 | ffe_coeff_set12_bankC_float1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [11:08] RW/V |
ffe_coeff_set12_bankC_float3 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set12_bankC_float2 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set12_bankC_float1 Reset: hex:0x0; |
+0x00000108 Register(32 bit) ffe_coeff_set13_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e108 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x0000c0c0 | ||
| Undefined | 0x0000c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set13_coeff_post1 | ffe_coeff_set13_coeff_pre1 | - | ffe_coeff_set13_coeff_pre2 | - | ffe_coeff_set13_coeff_pre3 | ||||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set13_coeff_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set13_coeff_pre1 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set13_coeff_pre2 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set13_coeff_pre3 Reset: hex:0x00; |
+0x0000010c Register(32 bit) ffe_coeff_set13_1
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e10c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c000 | ||
| Undefined | 0xc0c0c000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set13_coeff_post5 | - | ffe_coeff_set13_coeff_post4 | - | ffe_coeff_set13_coeff_post3 | ffe_coeff_set13_coeff_post2 | |||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | RW/V | |||||||||||||||||||||||||
| [29:24] RW/V |
ffe_coeff_set13_coeff_post5 Reset: hex:0x00; |
| [21:16] RW/V |
ffe_coeff_set13_coeff_post4 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set13_coeff_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set13_coeff_post2 Reset: hex:0x00; |
+0x00000110 Register(32 bit) ffe_coeff_set13_2
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e110 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00c0c0c0 | ||
| Undefined | 0x00c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set13_coeff_post10 | ffe_coeff_set13_coeff_post9 | - | ffe_coeff_set13_coeff_post8 | - | ffe_coeff_set13_coeff_post7 | - | ffe_coeff_set13_coeff_post6 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set13_coeff_post10 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set13_coeff_post9 Reset: hex:0x0; |
| [21:16] RW/V |
ffe_coeff_set13_coeff_post8 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set13_coeff_post7 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set13_coeff_post6 Reset: hex:0x00; |
+0x00000114 Register(32 bit) ffe_coeff_set13_3
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e114 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set13_bankB_float3 | ffe_coeff_set13_bankB_float2 | ffe_coeff_set13_bankB_float1 | ffe_coeff_set13_bankA_float3 | ffe_coeff_set13_bankA_float2 | ffe_coeff_set13_bankA_float1 | ffe_coeff_set13_coeff_post12 | ffe_coeff_set13_coeff_post11 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set13_bankB_float3 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set13_bankB_float2 Reset: hex:0x0; |
| [23:20] RW/V |
ffe_coeff_set13_bankB_float1 Reset: hex:0x0; |
| [19:16] RW/V |
ffe_coeff_set13_bankA_float3 Reset: hex:0x0; |
| [15:12] RW/V |
ffe_coeff_set13_bankA_float2 Reset: hex:0x0; |
| [11:08] RW/V |
ffe_coeff_set13_bankA_float1 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set13_coeff_post12 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set13_coeff_post11 Reset: hex:0x0; |
+0x00000118 Register(32 bit) ffe_coeff_set13_4
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e118 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffff000 | ||
| Undefined | 0xfffff000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set13_bankC_float3 | ffe_coeff_set13_bankC_float2 | ffe_coeff_set13_bankC_float1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [11:08] RW/V |
ffe_coeff_set13_bankC_float3 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set13_bankC_float2 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set13_bankC_float1 Reset: hex:0x0; |
+0x0000011c Register(32 bit) ffe_coeff_set14_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e11c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x0000c0c0 | ||
| Undefined | 0x0000c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set14_coeff_post1 | ffe_coeff_set14_coeff_pre1 | - | ffe_coeff_set14_coeff_pre2 | - | ffe_coeff_set14_coeff_pre3 | ||||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set14_coeff_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set14_coeff_pre1 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set14_coeff_pre2 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set14_coeff_pre3 Reset: hex:0x00; |
+0x00000120 Register(32 bit) ffe_coeff_set14_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e120 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c000 | ||
| Undefined | 0xc0c0c000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set14_coeff_post5 | - | ffe_coeff_set14_coeff_post4 | - | ffe_coeff_set14_coeff_post3 | ffe_coeff_set14_coeff_post2 | |||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | RW/V | |||||||||||||||||||||||||
| [29:24] RW/V |
ffe_coeff_set14_coeff_post5 Reset: hex:0x00; |
| [21:16] RW/V |
ffe_coeff_set14_coeff_post4 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set14_coeff_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set14_coeff_post2 Reset: hex:0x00; |
+0x00000124 Register(32 bit) ffe_coeff_set14_2
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e124 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00c0c0c0 | ||
| Undefined | 0x00c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set14_coeff_post10 | ffe_coeff_set14_coeff_post9 | - | ffe_coeff_set14_coeff_post8 | - | ffe_coeff_set14_coeff_post7 | - | ffe_coeff_set14_coeff_post6 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set14_coeff_post10 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set14_coeff_post9 Reset: hex:0x0; |
| [21:16] RW/V |
ffe_coeff_set14_coeff_post8 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set14_coeff_post7 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set14_coeff_post6 Reset: hex:0x00; |
+0x00000128 Register(32 bit) ffe_coeff_set14_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e128 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set14_bankB_float3 | ffe_coeff_set14_bankB_float2 | ffe_coeff_set14_bankB_float1 | ffe_coeff_set14_bankA_float3 | ffe_coeff_set14_bankA_float2 | ffe_coeff_set14_bankA_float1 | ffe_coeff_set14_coeff_post12 | ffe_coeff_set14_coeff_post11 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set14_bankB_float3 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set14_bankB_float2 Reset: hex:0x0; |
| [23:20] RW/V |
ffe_coeff_set14_bankB_float1 Reset: hex:0x0; |
| [19:16] RW/V |
ffe_coeff_set14_bankA_float3 Reset: hex:0x0; |
| [15:12] RW/V |
ffe_coeff_set14_bankA_float2 Reset: hex:0x0; |
| [11:08] RW/V |
ffe_coeff_set14_bankA_float1 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set14_coeff_post12 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set14_coeff_post11 Reset: hex:0x0; |
+0x0000012c Register(32 bit) ffe_coeff_set14_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e12c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffff000 | ||
| Undefined | 0xfffff000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set14_bankC_float3 | ffe_coeff_set14_bankC_float2 | ffe_coeff_set14_bankC_float1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [11:08] RW/V |
ffe_coeff_set14_bankC_float3 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set14_bankC_float2 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set14_bankC_float1 Reset: hex:0x0; |
+0x00000130 Register(32 bit) ffe_coeff_set15_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e130 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x0000c0c0 | ||
| Undefined | 0x0000c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set15_coeff_post1 | ffe_coeff_set15_coeff_pre1 | - | ffe_coeff_set15_coeff_pre2 | - | ffe_coeff_set15_coeff_pre3 | ||||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set15_coeff_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set15_coeff_pre1 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set15_coeff_pre2 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set15_coeff_pre3 Reset: hex:0x00; |
+0x00000134 Register(32 bit) ffe_coeff_set15_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e134 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c000 | ||
| Undefined | 0xc0c0c000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set15_coeff_post5 | - | ffe_coeff_set15_coeff_post4 | - | ffe_coeff_set15_coeff_post3 | ffe_coeff_set15_coeff_post2 | |||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | RW/V | |||||||||||||||||||||||||
| [29:24] RW/V |
ffe_coeff_set15_coeff_post5 Reset: hex:0x00; |
| [21:16] RW/V |
ffe_coeff_set15_coeff_post4 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set15_coeff_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set15_coeff_post2 Reset: hex:0x00; |
+0x00000138 Register(32 bit) ffe_coeff_set15_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e138 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00c0c0c0 | ||
| Undefined | 0x00c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set15_coeff_post10 | ffe_coeff_set15_coeff_post9 | - | ffe_coeff_set15_coeff_post8 | - | ffe_coeff_set15_coeff_post7 | - | ffe_coeff_set15_coeff_post6 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set15_coeff_post10 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set15_coeff_post9 Reset: hex:0x0; |
| [21:16] RW/V |
ffe_coeff_set15_coeff_post8 Reset: hex:0x00; |
| [13:08] RW/V |
ffe_coeff_set15_coeff_post7 Reset: hex:0x00; |
| [05:00] RW/V |
ffe_coeff_set15_coeff_post6 Reset: hex:0x00; |
+0x0000013c Register(32 bit) ffe_coeff_set15_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e13c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set15_bankB_float3 | ffe_coeff_set15_bankB_float2 | ffe_coeff_set15_bankB_float1 | ffe_coeff_set15_bankA_float3 | ffe_coeff_set15_bankA_float2 | ffe_coeff_set15_bankA_float1 | ffe_coeff_set15_coeff_post12 | ffe_coeff_set15_coeff_post11 | ||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||
| [31:28] RW/V |
ffe_coeff_set15_bankB_float3 Reset: hex:0x0; |
| [27:24] RW/V |
ffe_coeff_set15_bankB_float2 Reset: hex:0x0; |
| [23:20] RW/V |
ffe_coeff_set15_bankB_float1 Reset: hex:0x0; |
| [19:16] RW/V |
ffe_coeff_set15_bankA_float3 Reset: hex:0x0; |
| [15:12] RW/V |
ffe_coeff_set15_bankA_float2 Reset: hex:0x0; |
| [11:08] RW/V |
ffe_coeff_set15_bankA_float1 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set15_coeff_post12 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set15_coeff_post11 Reset: hex:0x0; |
+0x00000140 Register(32 bit) ffe_coeff_set15_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e140 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffff000 | ||
| Undefined | 0xfffff000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coeff_set15_bankC_float3 | ffe_coeff_set15_bankC_float2 | ffe_coeff_set15_bankC_float1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [11:08] RW/V |
ffe_coeff_set15_bankC_float3 Reset: hex:0x0; |
| [07:04] RW/V |
ffe_coeff_set15_bankC_float2 Reset: hex:0x0; |
| [03:00] RW/V |
ffe_coeff_set15_bankC_float1 Reset: hex:0x0; |
+0x00000148 Register(32 bit) ffe_slice_level_set0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e148 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x2b000150 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_slice_level_set0_m1 | ffe_slice_level_set0_0 | ffe_slice_level_set0_p1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ffe_slice_level_set0_m1 Reset: hex:0x2b0; |
| [19:10] RW/V |
ffe_slice_level_set0_0 Reset: hex:0x000; |
| [09:00] RW/V |
ffe_slice_level_set0_p1 Reset: hex:0x150; |
+0x0000014c Register(32 bit) ffe_slice_level_set1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e14c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x2b000150 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_slice_level_set1_m1 | ffe_slice_level_set1_0 | ffe_slice_level_set1_p1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ffe_slice_level_set1_m1 Reset: hex:0x2b0; |
| [19:10] RW/V |
ffe_slice_level_set1_0 Reset: hex:0x000; |
| [09:00] RW/V |
ffe_slice_level_set1_p1 Reset: hex:0x150; |
+0x00000150 Register(32 bit) ffe_slice_level_set2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e150 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x2b000150 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_slice_level_set2_m1 | ffe_slice_level_set2_0 | ffe_slice_level_set2_p1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ffe_slice_level_set2_m1 Reset: hex:0x2b0; |
| [19:10] RW/V |
ffe_slice_level_set2_0 Reset: hex:0x000; |
| [09:00] RW/V |
ffe_slice_level_set2_p1 Reset: hex:0x150; |
+0x00000154 Register(32 bit) ffe_slice_level_set3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e154 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x2b000150 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_slice_level_set3_m1 | ffe_slice_level_set3_0 | ffe_slice_level_set3_p1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ffe_slice_level_set3_m1 Reset: hex:0x2b0; |
| [19:10] RW/V |
ffe_slice_level_set3_0 Reset: hex:0x000; |
| [09:00] RW/V |
ffe_slice_level_set3_p1 Reset: hex:0x150; |
+0x00000158 Register(32 bit) ffe_slice_level_set4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e158 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x2b000150 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_slice_level_set4_m1 | ffe_slice_level_set4_0 | ffe_slice_level_set4_p1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ffe_slice_level_set4_m1 Reset: hex:0x2b0; |
| [19:10] RW/V |
ffe_slice_level_set4_0 Reset: hex:0x000; |
| [09:00] RW/V |
ffe_slice_level_set4_p1 Reset: hex:0x150; |
+0x0000015c Register(32 bit) ffe_slice_level_set5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e15c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x2b000150 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_slice_level_set5_m1 | ffe_slice_level_set5_0 | ffe_slice_level_set5_p1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ffe_slice_level_set5_m1 Reset: hex:0x2b0; |
| [19:10] RW/V |
ffe_slice_level_set5_0 Reset: hex:0x000; |
| [09:00] RW/V |
ffe_slice_level_set5_p1 Reset: hex:0x150; |
+0x00000160 Register(32 bit) ffe_slice_level_set6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e160 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x2b000150 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_slice_level_set6_m1 | ffe_slice_level_set6_0 | ffe_slice_level_set6_p1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ffe_slice_level_set6_m1 Reset: hex:0x2b0; |
| [19:10] RW/V |
ffe_slice_level_set6_0 Reset: hex:0x000; |
| [09:00] RW/V |
ffe_slice_level_set6_p1 Reset: hex:0x150; |
+0x00000164 Register(32 bit) ffe_slice_level_set7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e164 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x2b000150 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_slice_level_set7_m1 | ffe_slice_level_set7_0 | ffe_slice_level_set7_p1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ffe_slice_level_set7_m1 Reset: hex:0x2b0; |
| [19:10] RW/V |
ffe_slice_level_set7_0 Reset: hex:0x000; |
| [09:00] RW/V |
ffe_slice_level_set7_p1 Reset: hex:0x150; |
+0x00000168 Register(32 bit) ffe_slice_level_set8
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e168 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x2b000150 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_slice_level_set8_m1 | ffe_slice_level_set8_0 | ffe_slice_level_set8_p1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ffe_slice_level_set8_m1 Reset: hex:0x2b0; |
| [19:10] RW/V |
ffe_slice_level_set8_0 Reset: hex:0x000; |
| [09:00] RW/V |
ffe_slice_level_set8_p1 Reset: hex:0x150; |
+0x0000016c Register(32 bit) ffe_slice_level_set9
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e16c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x2b000150 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_slice_level_set9_m1 | ffe_slice_level_set9_0 | ffe_slice_level_set9_p1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ffe_slice_level_set9_m1 Reset: hex:0x2b0; |
| [19:10] RW/V |
ffe_slice_level_set9_0 Reset: hex:0x000; |
| [09:00] RW/V |
ffe_slice_level_set9_p1 Reset: hex:0x150; |
+0x00000170 Register(32 bit) ffe_slice_level_set10
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e170 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x2b000150 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_slice_level_set10_m1 | ffe_slice_level_set10_0 | ffe_slice_level_set10_p1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ffe_slice_level_set10_m1 Reset: hex:0x2b0; |
| [19:10] RW/V |
ffe_slice_level_set10_0 Reset: hex:0x000; |
| [09:00] RW/V |
ffe_slice_level_set10_p1 Reset: hex:0x150; |
+0x00000174 Register(32 bit) ffe_slice_level_set11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e174 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x2b000150 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_slice_level_set11_m1 | ffe_slice_level_set11_0 | ffe_slice_level_set11_p1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ffe_slice_level_set11_m1 Reset: hex:0x2b0; |
| [19:10] RW/V |
ffe_slice_level_set11_0 Reset: hex:0x000; |
| [09:00] RW/V |
ffe_slice_level_set11_p1 Reset: hex:0x150; |
+0x00000178 Register(32 bit) ffe_slice_level_set12
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e178 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x2b000150 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_slice_level_set12_m1 | ffe_slice_level_set12_0 | ffe_slice_level_set12_p1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ffe_slice_level_set12_m1 Reset: hex:0x2b0; |
| [19:10] RW/V |
ffe_slice_level_set12_0 Reset: hex:0x000; |
| [09:00] RW/V |
ffe_slice_level_set12_p1 Reset: hex:0x150; |
+0x0000017c Register(32 bit) ffe_slice_level_set13
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e17c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x2b000150 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_slice_level_set13_m1 | ffe_slice_level_set13_0 | ffe_slice_level_set13_p1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ffe_slice_level_set13_m1 Reset: hex:0x2b0; |
| [19:10] RW/V |
ffe_slice_level_set13_0 Reset: hex:0x000; |
| [09:00] RW/V |
ffe_slice_level_set13_p1 Reset: hex:0x150; |
+0x00000180 Register(32 bit) ffe_slice_level_set14
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e180 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x2b000150 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_slice_level_set14_m1 | ffe_slice_level_set14_0 | ffe_slice_level_set14_p1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ffe_slice_level_set14_m1 Reset: hex:0x2b0; |
| [19:10] RW/V |
ffe_slice_level_set14_0 Reset: hex:0x000; |
| [09:00] RW/V |
ffe_slice_level_set14_p1 Reset: hex:0x150; |
+0x00000184 Register(32 bit) ffe_slice_level_set15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e184 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x2b000150 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_slice_level_set15_m1 | ffe_slice_level_set15_0 | ffe_slice_level_set15_p1 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ffe_slice_level_set15_m1 Reset: hex:0x2b0; |
| [19:10] RW/V |
ffe_slice_level_set15_0 Reset: hex:0x000; |
| [09:00] RW/V |
ffe_slice_level_set15_p1 Reset: hex:0x150; |
+0x00000188 Register(32 bit) ffe_err_level_m1m3_set0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e188 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00082350 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set0_m3 | ffe_err_level_set0_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set0_m3 Reset: hex:0x208; |
| [09:00] RW/V |
ffe_err_level_set0_m1 Reset: hex:0x350; |
+0x0000018c Register(32 bit) ffe_err_level_p1p3_set0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e18c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0007e0b0 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set0_p3 | ffe_err_level_set0_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set0_p3 Reset: hex:0x1f8; |
| [09:00] RW/V |
ffe_err_level_set0_p1 Reset: hex:0x0b0; |
+0x00000190 Register(32 bit) ffe_err_level_m1m3_set1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e190 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00082350 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set1_m3 | ffe_err_level_set1_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set1_m3 Reset: hex:0x208; |
| [09:00] RW/V |
ffe_err_level_set1_m1 Reset: hex:0x350; |
+0x00000194 Register(32 bit) ffe_err_level_p1p3_set1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e194 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0007e0b0 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set1_p3 | ffe_err_level_set1_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set1_p3 Reset: hex:0x1f8; |
| [09:00] RW/V |
ffe_err_level_set1_p1 Reset: hex:0x0b0; |
+0x00000198 Register(32 bit) ffe_err_level_m1m3_set2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e198 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00082350 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set2_m3 | ffe_err_level_set2_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set2_m3 Reset: hex:0x208; |
| [09:00] RW/V |
ffe_err_level_set2_m1 Reset: hex:0x350; |
+0x0000019c Register(32 bit) ffe_err_level_p1p3_set2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e19c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0007e0b0 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set2_p3 | ffe_err_level_set2_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set2_p3 Reset: hex:0x1f8; |
| [09:00] RW/V |
ffe_err_level_set2_p1 Reset: hex:0x0b0; |
+0x000001a0 Register(32 bit) ffe_err_level_m1m3_set3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1a0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00082350 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set3_m3 | ffe_err_level_set3_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set3_m3 Reset: hex:0x208; |
| [09:00] RW/V |
ffe_err_level_set3_m1 Reset: hex:0x350; |
+0x000001a4 Register(32 bit) ffe_err_level_p1p3_set3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1a4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0007e0b0 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set3_p3 | ffe_err_level_set3_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set3_p3 Reset: hex:0x1f8; |
| [09:00] RW/V |
ffe_err_level_set3_p1 Reset: hex:0x0b0; |
+0x000001a8 Register(32 bit) ffe_err_level_m1m3_set4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1a8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00082350 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set4_m3 | ffe_err_level_set4_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set4_m3 Reset: hex:0x208; |
| [09:00] RW/V |
ffe_err_level_set4_m1 Reset: hex:0x350; |
+0x000001ac Register(32 bit) ffe_err_level_p1p3_set4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1ac at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0007e0b0 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set4_p3 | ffe_err_level_set4_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set4_p3 Reset: hex:0x1f8; |
| [09:00] RW/V |
ffe_err_level_set4_p1 Reset: hex:0x0b0; |
+0x000001b0 Register(32 bit) ffe_err_level_m1m3_set5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1b0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00082350 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set5_m3 | ffe_err_level_set5_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set5_m3 Reset: hex:0x208; |
| [09:00] RW/V |
ffe_err_level_set5_m1 Reset: hex:0x350; |
+0x000001b4 Register(32 bit) ffe_err_level_p1p3_set5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1b4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0007e0b0 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set5_p3 | ffe_err_level_set5_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set5_p3 Reset: hex:0x1f8; |
| [09:00] RW/V |
ffe_err_level_set5_p1 Reset: hex:0x0b0; |
+0x000001b8 Register(32 bit) ffe_err_level_m1m3_set6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1b8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00082350 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set6_m3 | ffe_err_level_set6_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set6_m3 Reset: hex:0x208; |
| [09:00] RW/V |
ffe_err_level_set6_m1 Reset: hex:0x350; |
+0x000001bc Register(32 bit) ffe_err_level_p1p3_set6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1bc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0007e0b0 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set6_p3 | ffe_err_level_set6_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set6_p3 Reset: hex:0x1f8; |
| [09:00] RW/V |
ffe_err_level_set6_p1 Reset: hex:0x0b0; |
+0x000001c0 Register(32 bit) ffe_err_level_m1m3_set7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1c0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00082350 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set7_m3 | ffe_err_level_set7_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set7_m3 Reset: hex:0x208; |
| [09:00] RW/V |
ffe_err_level_set7_m1 Reset: hex:0x350; |
+0x000001c4 Register(32 bit) ffe_err_level_p1p3_set7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1c4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0007e0b0 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set7_p3 | ffe_err_level_set7_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set7_p3 Reset: hex:0x1f8; |
| [09:00] RW/V |
ffe_err_level_set7_p1 Reset: hex:0x0b0; |
+0x000001c8 Register(32 bit) ffe_err_level_m1m3_set8
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1c8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00082350 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set8_m3 | ffe_err_level_set8_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set8_m3 Reset: hex:0x208; |
| [09:00] RW/V |
ffe_err_level_set8_m1 Reset: hex:0x350; |
+0x000001cc Register(32 bit) ffe_err_level_p1p3_set8
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1cc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0007e0b0 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set8_p3 | ffe_err_level_set8_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set8_p3 Reset: hex:0x1f8; |
| [09:00] RW/V |
ffe_err_level_set8_p1 Reset: hex:0x0b0; |
+0x000001d0 Register(32 bit) ffe_err_level_m1m3_set9
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1d0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00082350 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set9_m3 | ffe_err_level_set9_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set9_m3 Reset: hex:0x208; |
| [09:00] RW/V |
ffe_err_level_set9_m1 Reset: hex:0x350; |
+0x000001d4 Register(32 bit) ffe_err_level_p1p3_set9
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1d4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0007e0b0 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set9_p3 | ffe_err_level_set9_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set9_p3 Reset: hex:0x1f8; |
| [09:00] RW/V |
ffe_err_level_set9_p1 Reset: hex:0x0b0; |
+0x000001d8 Register(32 bit) ffe_err_level_m1m3_set10
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1d8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00082350 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set10_m3 | ffe_err_level_set10_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set10_m3 Reset: hex:0x208; |
| [09:00] RW/V |
ffe_err_level_set10_m1 Reset: hex:0x350; |
+0x000001dc Register(32 bit) ffe_err_level_p1p3_set10
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1dc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0007e0b0 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set10_p3 | ffe_err_level_set10_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set10_p3 Reset: hex:0x1f8; |
| [09:00] RW/V |
ffe_err_level_set10_p1 Reset: hex:0x0b0; |
+0x000001e0 Register(32 bit) ffe_err_level_m1m3_set11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1e0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00082350 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set11_m3 | ffe_err_level_set11_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set11_m3 Reset: hex:0x208; |
| [09:00] RW/V |
ffe_err_level_set11_m1 Reset: hex:0x350; |
+0x000001e4 Register(32 bit) ffe_err_level_p1p3_set11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1e4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0007e0b0 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set11_p3 | ffe_err_level_set11_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set11_p3 Reset: hex:0x1f8; |
| [09:00] RW/V |
ffe_err_level_set11_p1 Reset: hex:0x0b0; |
+0x000001e8 Register(32 bit) ffe_err_level_m1m3_set12
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1e8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00082350 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set12_m3 | ffe_err_level_set12_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set12_m3 Reset: hex:0x208; |
| [09:00] RW/V |
ffe_err_level_set12_m1 Reset: hex:0x350; |
+0x000001ec Register(32 bit) ffe_err_level_p1p3_set12
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1ec at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0007e0b0 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set12_p3 | ffe_err_level_set12_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set12_p3 Reset: hex:0x1f8; |
| [09:00] RW/V |
ffe_err_level_set12_p1 Reset: hex:0x0b0; |
+0x000001f0 Register(32 bit) ffe_err_level_m1m3_set13
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1f0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00082350 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set13_m3 | ffe_err_level_set13_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set13_m3 Reset: hex:0x208; |
| [09:00] RW/V |
ffe_err_level_set13_m1 Reset: hex:0x350; |
+0x000001f4 Register(32 bit) ffe_err_level_p1p3_set13
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1f4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0007e0b0 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set13_p3 | ffe_err_level_set13_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set13_p3 Reset: hex:0x1f8; |
| [09:00] RW/V |
ffe_err_level_set13_p1 Reset: hex:0x0b0; |
+0x000001f8 Register(32 bit) ffe_err_level_m1m3_set14
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1f8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00082350 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set14_m3 | ffe_err_level_set14_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set14_m3 Reset: hex:0x208; |
| [09:00] RW/V |
ffe_err_level_set14_m1 Reset: hex:0x350; |
+0x000001fc Register(32 bit) ffe_err_level_p1p3_set14
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e1fc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0007e0b0 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set14_p3 | ffe_err_level_set14_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set14_p3 Reset: hex:0x1f8; |
| [09:00] RW/V |
ffe_err_level_set14_p1 Reset: hex:0x0b0; |
+0x00000200 Register(32 bit) ffe_err_level_m1m3_set15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e200 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00082350 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set15_m3 | ffe_err_level_set15_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set15_m3 Reset: hex:0x208; |
| [09:00] RW/V |
ffe_err_level_set15_m1 Reset: hex:0x350; |
+0x00000204 Register(32 bit) ffe_err_level_p1p3_set15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e204 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0007e0b0 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_err_level_set15_p3 | ffe_err_level_set15_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [19:10] RW/V |
ffe_err_level_set15_p3 Reset: hex:0x1f8; |
| [09:00] RW/V |
ffe_err_level_set15_p1 Reset: hex:0x0b0; |
+0x00000208 Register(32 bit) rx_dump_mem_ctrl
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e208 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xffffffc0 | ||
| Undefined | 0xffffffc0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | dump_mem_src_sel | adc_dump_wait_for_rx_rdy | adc_dump_mem_en | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [05:02] RW |
dump_mem_src_sel Reset: hex:0x0; |
| [01:01] RW |
adc_dump_wait_for_rx_rdy Reset: hex:0x0; |
| [00:00] RW |
adc_dump_mem_en Reset: hex:0x0; |
+0x0000020c Register(32 bit) rx_dump_mem_apb_rd_data
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e20c at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | rx_dump_mem_apb_rd_data | |||||||||||||||||||||||||||||||
| Access | RO/V | |||||||||||||||||||||||||||||||
| [31:00] RO/V |
rx_dump_mem_apb_rd_data Reset: hex:0x00000000; |
+0x00000210 Register(32 bit) rx_dump_mem_apb_rd_en
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e210 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffffffe | ||
| Undefined | 0xfffffffe | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 |
| Name | - | rx_dump_mem_apb_rd_en | ||||||||||||||||||||||||||||||
| Access | - | RW | ||||||||||||||||||||||||||||||
| [00:00] RW |
rx_dump_mem_apb_rd_en Reset: hex:0x0; |
+0x00000214 Register(32 bit) rx_dump_mem_apb_en
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e214 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000018 | |
| Unaffected | 0xffffffe0 | ||
| Undefined | 0xffffffe0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 1 | 0 | 0 | 0 |
| Name | - | rx_dump_mem_num_trans | rx_dump_mem_apb_en | |||||||||||||||||||||||||||||
| Access | - | RW | RW | |||||||||||||||||||||||||||||
| [04:01] RW |
rx_dump_mem_num_trans Reset: hex:0xc; |
| [00:00] RW |
rx_dump_mem_apb_en Reset: hex:0x0; |
+0x00000218 Register(32 bit) rx_data_path_control_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e218 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff001800 | ||
| Undefined | 0xff001800 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_vref_mu_boost | cdr_vref_mu_boost | adc_vref_mu_boost | cdr_phdt_update_dis | cdr_phdt_src_sel | hist_cdr_voters_sel | hist_src_sel | - | rx_adc_0_code_replace | datapath_data_source_sel | cdr_ffe_slice_inv_p_err | cdr_ffe_slice_inv_n_err | adc_slice_inv_p_err | adc_slice_inv_n_err | ffe_slice_inv_p_err | ffe_slice_inv_n_err | |||||||||||||||
| Access | - | RW | RW | RW | RW | RW | RW | RW | - | RW | RW | RW | RW | RW | RW | RW | RW | |||||||||||||||
| [23:22] RW |
ffe_vref_mu_boost Reset: hex:0x0; |
| [21:20] RW |
cdr_vref_mu_boost Reset: hex:0x0; |
| [19:18] RW |
adc_vref_mu_boost Reset: hex:0x0; |
| [17:17] RW |
cdr_phdt_update_dis Reset: hex:0x0; |
| [16:16] RW |
cdr_phdt_src_sel Reset: hex:0x0; |
| [15:15] RW |
hist_cdr_voters_sel Reset: hex:0x0; |
| [14:13] RW |
hist_src_sel Reset: hex:0x0; |
| [10:08] RW |
rx_adc_0_code_replace Reset: hex:0x0; |
| [07:06] RW |
datapath_data_source_sel Reset: hex:0x0; |
| [05:05] RW |
cdr_ffe_slice_inv_p_err Reset: hex:0x0; |
| [04:04] RW |
cdr_ffe_slice_inv_n_err Reset: hex:0x0; |
| [03:03] RW |
adc_slice_inv_p_err Reset: hex:0x0; |
| [02:02] RW |
adc_slice_inv_n_err Reset: hex:0x0; |
| [01:01] RW |
ffe_slice_inv_p_err Reset: hex:0x0; |
| [00:00] RW |
ffe_slice_inv_n_err Reset: hex:0x0; |
+0x0000021c Register(32 bit) adp_msb_lsb_swap_ctrl
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e21c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000003 | |
| Unaffected | 0xfc000010 | ||
| Undefined | 0xfc000010 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 1 | 1 |
| Name | - | hist_compr_swap | ffe_filter_msb_inv_cb | ffe_in_msb_inv_cb | - | cdr_ffe_in_msb_inv_cb | lms_msb_inv_cb | dp_src_sel_msb_newest_en | fs_lsb_newest_en | |||||||||||||||||||||||
| Access | - | RW | RW | RW | - | RW | RW | RW | RW | |||||||||||||||||||||||
| [25:07] RW |
hist_compr_swap Reset: hex:0x00000; |
| [06:06] RW |
ffe_filter_msb_inv_cb Reset: hex:0x0; |
| [05:05] RW |
ffe_in_msb_inv_cb Reset: hex:0x0; |
| [03:03] RW |
cdr_ffe_in_msb_inv_cb Reset: hex:0x0; |
| [02:02] RW |
lms_msb_inv_cb Reset: hex:0x0; |
| [01:01] RW |
dp_src_sel_msb_newest_en Reset: hex:0x1; |
| [00:00] RW |
fs_lsb_newest_en Reset: hex:0x1; |
+0x00000220 Register(32 bit) ffe_float_tap_position1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e220 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x03020100 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 1 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | float_tap_3_position | - | float_tap_2_position | - | float_tap_1_position | - | float_tap_0_position | ||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | - | RW | ||||||||||||||||||||||||
| [29:24] RW |
float_tap_3_position Reset: hex:0x03; |
| [21:16] RW |
float_tap_2_position Reset: hex:0x02; |
| [13:08] RW |
float_tap_1_position Reset: hex:0x01; |
| [05:00] RW |
float_tap_0_position Reset: hex:0x00; |
+0x00000224 Register(32 bit) ffe_float_tap_position2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e224 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x07060504 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 1 | 1 | 1 | - | - | 0 | 0 | 0 | 1 | 1 | 0 | - | - | 0 | 0 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 0 | 1 | 0 | 0 |
| Name | - | float_tap_7_position | - | float_tap_6_position | - | float_tap_5_position | - | float_tap_4_position | ||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | - | RW | ||||||||||||||||||||||||
| [29:24] RW |
float_tap_7_position Reset: hex:0x07; |
| [21:16] RW |
float_tap_6_position Reset: hex:0x06; |
| [13:08] RW |
float_tap_5_position Reset: hex:0x05; |
| [05:00] RW |
float_tap_4_position Reset: hex:0x04; |
+0x00000228 Register(32 bit) ffe_float_tap_position3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e228 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000008 | |
| Unaffected | 0xffffffc0 | ||
| Undefined | 0xffffffc0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 1 | 0 | 0 | 0 |
| Name | - | float_tap_8_position | ||||||||||||||||||||||||||||||
| Access | - | RW | ||||||||||||||||||||||||||||||
| [05:00] RW |
float_tap_8_position Reset: hex:0x08; |
+0x0000022c Register(32 bit) rxeq_clock_gating_ctrl_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e22c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_gated_0 | |||||||||||||||||||||||||||||||
| Access | RW | |||||||||||||||||||||||||||||||
| [31:00] RW |
ffe_gated_0 Reset: hex:0x00000000; |
+0x00000230 Register(32 bit) rxeq_clock_gating_ctrl_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e230 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_gated_1 | |||||||||||||||||||||||||||||||
| Access | RW | |||||||||||||||||||||||||||||||
| [31:00] RW |
ffe_gated_1 Reset: hex:0x00000000; |
+0x00000234 Register(32 bit) rxeq_clock_gating_ctrl_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e234 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_lms_gated | ||||||||||||||||||||||||||||||
| Access | - | RW | ||||||||||||||||||||||||||||||
| [23:00] RW |
ffe_lms_gated Reset: hex:0x000000; |
+0x00000238 Register(32 bit) rxeq_clock_gating_ctrl_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e238 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | dfe_windowing_gated | dfe_lms_gated | ofc_lms_gated | adcofc_lms_gated | vga_lms_gated | hst_lms_gated | affe_lms_gated | adcvref_lms_gated | dfe_64la_gated | edgvref_lms_gated | vref_lms_gated | |||||||||||||||||||||
| Access | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | |||||||||||||||||||||
| [31:31] RW |
dfe_windowing_gated Reset: hex:0x0; |
| [30:30] RW |
dfe_lms_gated Reset: hex:0x0; |
| [29:24] RW |
ofc_lms_gated Reset: hex:0x00; |
| [23:18] RW |
adcofc_lms_gated Reset: hex:0x00; |
| [17:17] RW |
vga_lms_gated Reset: hex:0x0; |
| [16:16] RW |
hst_lms_gated Reset: hex:0x0; |
| [15:12] RW |
affe_lms_gated Reset: hex:0x0; |
| [11:08] RW |
adcvref_lms_gated Reset: hex:0x0; |
| [07:07] RW |
dfe_64la_gated Reset: hex:0x0; |
| [06:04] RW |
edgvref_lms_gated Reset: hex:0x0; |
| [03:00] RW |
vref_lms_gated Reset: hex:0x0; |
+0x0000023c Register(32 bit) rxeq_clock_gating_ctrl_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e23c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xffffff00 | ||
| Undefined | 0xffffff00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ops_lms_gated | ||||||||||||||||||||||||||||||
| Access | - | RW | ||||||||||||||||||||||||||||||
| [07:00] RW |
ops_lms_gated Reset: hex:0x00; |
+0x00000240 Register(32 bit) rxeq_clock_gating_ctrl_6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e240 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_gated_0 | |||||||||||||||||||||||||||||||
| Access | RW | |||||||||||||||||||||||||||||||
| [31:00] RW |
cdr_ffe_gated_0 Reset: hex:0x00000000; |
+0x00000244 Register(32 bit) rxeq_clock_gating_ctrl_7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e244 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_gated_1 | |||||||||||||||||||||||||||||||
| Access | RW | |||||||||||||||||||||||||||||||
| [31:00] RW |
cdr_ffe_gated_1 Reset: hex:0x00000000; |
+0x00000248 Register(32 bit) rxeq_clock_gating_ctrl_8
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e248 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffc0080 | ||
| Undefined | 0xfffc0080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_vref_lms_gated | cdr_ffe_ofc_lms_gated | - | cdr_ffe_lms_gated | |||||||||||||||||||||||||||
| Access | - | RW | RW | - | RW | |||||||||||||||||||||||||||
| [17:14] RW |
cdr_ffe_vref_lms_gated Reset: hex:0x0; |
| [13:08] RW |
cdr_ffe_ofc_lms_gated Reset: hex:0x00; |
| [06:00] RW |
cdr_ffe_lms_gated Reset: hex:0x00; |
+0x0000028c Register(32 bit) adc_slicer_level_set0_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e28c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x002b0015 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 1 | 0 | 1 |
| Name | - | adc_slice_level_set0_m1 | - | adc_slice_level_set0_0 | - | adc_slice_level_set0_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adc_slice_level_set0_m1 Reset: hex:0x2b; |
| [13:08] RW/V |
adc_slice_level_set0_0 Reset: hex:0x00; |
| [05:00] RW/V |
adc_slice_level_set0_p1 Reset: hex:0x15; |
+0x00000290 Register(32 bit) adc_slicer_level_set1_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e290 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x002b0015 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 1 | 0 | 1 |
| Name | - | adc_slice_level_set1_m1 | - | adc_slice_level_set1_0 | - | adc_slice_level_set1_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adc_slice_level_set1_m1 Reset: hex:0x2b; |
| [13:08] RW/V |
adc_slice_level_set1_0 Reset: hex:0x00; |
| [05:00] RW/V |
adc_slice_level_set1_p1 Reset: hex:0x15; |
+0x00000294 Register(32 bit) adc_slicer_level_set2_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e294 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x002b0015 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 1 | 0 | 1 |
| Name | - | adc_slice_level_set2_m1 | - | adc_slice_level_set2_0 | - | adc_slice_level_set2_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adc_slice_level_set2_m1 Reset: hex:0x2b; |
| [13:08] RW/V |
adc_slice_level_set2_0 Reset: hex:0x00; |
| [05:00] RW/V |
adc_slice_level_set2_p1 Reset: hex:0x15; |
+0x00000298 Register(32 bit) adc_slicer_level_set3_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e298 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x002b0015 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 1 | 0 | 1 |
| Name | - | adc_slice_level_set3_m1 | - | adc_slice_level_set3_0 | - | adc_slice_level_set3_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adc_slice_level_set3_m1 Reset: hex:0x2b; |
| [13:08] RW/V |
adc_slice_level_set3_0 Reset: hex:0x00; |
| [05:00] RW/V |
adc_slice_level_set3_p1 Reset: hex:0x15; |
+0x0000029c Register(32 bit) adc_slicer_level_set4_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e29c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x002b0015 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 1 | 0 | 1 |
| Name | - | adc_slice_level_set4_m1 | - | adc_slice_level_set4_0 | - | adc_slice_level_set4_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adc_slice_level_set4_m1 Reset: hex:0x2b; |
| [13:08] RW/V |
adc_slice_level_set4_0 Reset: hex:0x00; |
| [05:00] RW/V |
adc_slice_level_set4_p1 Reset: hex:0x15; |
+0x000002a0 Register(32 bit) adc_slicer_level_set5_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2a0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x002b0015 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 1 | 0 | 1 |
| Name | - | adc_slice_level_set5_m1 | - | adc_slice_level_set5_0 | - | adc_slice_level_set5_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adc_slice_level_set5_m1 Reset: hex:0x2b; |
| [13:08] RW/V |
adc_slice_level_set5_0 Reset: hex:0x00; |
| [05:00] RW/V |
adc_slice_level_set5_p1 Reset: hex:0x15; |
+0x000002a4 Register(32 bit) adc_slicer_level_set6_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2a4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x002b0015 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 1 | 0 | 1 |
| Name | - | adc_slice_level_set6_m1 | - | adc_slice_level_set6_0 | - | adc_slice_level_set6_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adc_slice_level_set6_m1 Reset: hex:0x2b; |
| [13:08] RW/V |
adc_slice_level_set6_0 Reset: hex:0x00; |
| [05:00] RW/V |
adc_slice_level_set6_p1 Reset: hex:0x15; |
+0x000002a8 Register(32 bit) adc_slicer_level_set7_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2a8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x002b0015 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 1 | 0 | 1 |
| Name | - | adc_slice_level_set7_m1 | - | adc_slice_level_set7_0 | - | adc_slice_level_set7_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adc_slice_level_set7_m1 Reset: hex:0x2b; |
| [13:08] RW/V |
adc_slice_level_set7_0 Reset: hex:0x00; |
| [05:00] RW/V |
adc_slice_level_set7_p1 Reset: hex:0x15; |
+0x000002ac Register(32 bit) adc_slicer_level_set8_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2ac at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x002b0015 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 1 | 0 | 1 |
| Name | - | adc_slice_level_set8_m1 | - | adc_slice_level_set8_0 | - | adc_slice_level_set8_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adc_slice_level_set8_m1 Reset: hex:0x2b; |
| [13:08] RW/V |
adc_slice_level_set8_0 Reset: hex:0x00; |
| [05:00] RW/V |
adc_slice_level_set8_p1 Reset: hex:0x15; |
+0x000002b0 Register(32 bit) adc_slicer_level_set9_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2b0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x002b0015 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 1 | 0 | 1 |
| Name | - | adc_slice_level_set9_m1 | - | adc_slice_level_set9_0 | - | adc_slice_level_set9_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adc_slice_level_set9_m1 Reset: hex:0x2b; |
| [13:08] RW/V |
adc_slice_level_set9_0 Reset: hex:0x00; |
| [05:00] RW/V |
adc_slice_level_set9_p1 Reset: hex:0x15; |
+0x000002b4 Register(32 bit) adc_slicer_level_set10_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2b4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x002b0015 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 1 | 0 | 1 |
| Name | - | adc_slice_level_set10_m1 | - | adc_slice_level_set10_0 | - | adc_slice_level_set10_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adc_slice_level_set10_m1 Reset: hex:0x2b; |
| [13:08] RW/V |
adc_slice_level_set10_0 Reset: hex:0x00; |
| [05:00] RW/V |
adc_slice_level_set10_p1 Reset: hex:0x15; |
+0x000002b8 Register(32 bit) adc_slicer_level_set11_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2b8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x002b0015 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 1 | 0 | 1 |
| Name | - | adc_slice_level_set11_m1 | - | adc_slice_level_set11_0 | - | adc_slice_level_set11_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adc_slice_level_set11_m1 Reset: hex:0x2b; |
| [13:08] RW/V |
adc_slice_level_set11_0 Reset: hex:0x00; |
| [05:00] RW/V |
adc_slice_level_set11_p1 Reset: hex:0x15; |
+0x000002bc Register(32 bit) adc_slicer_level_set12_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2bc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x002b0015 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 1 | 0 | 1 |
| Name | - | adc_slice_level_set12_m1 | - | adc_slice_level_set12_0 | - | adc_slice_level_set12_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adc_slice_level_set12_m1 Reset: hex:0x2b; |
| [13:08] RW/V |
adc_slice_level_set12_0 Reset: hex:0x00; |
| [05:00] RW/V |
adc_slice_level_set12_p1 Reset: hex:0x15; |
+0x000002c0 Register(32 bit) adc_slicer_level_set13_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2c0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x002b0015 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 1 | 0 | 1 |
| Name | - | adc_slice_level_set13_m1 | - | adc_slice_level_set13_0 | - | adc_slice_level_set13_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adc_slice_level_set13_m1 Reset: hex:0x2b; |
| [13:08] RW/V |
adc_slice_level_set13_0 Reset: hex:0x00; |
| [05:00] RW/V |
adc_slice_level_set13_p1 Reset: hex:0x15; |
+0x000002c4 Register(32 bit) adc_slicer_level_set14_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2c4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x002b0015 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 1 | 0 | 1 |
| Name | - | adc_slice_level_set14_m1 | - | adc_slice_level_set14_0 | - | adc_slice_level_set14_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adc_slice_level_set14_m1 Reset: hex:0x2b; |
| [13:08] RW/V |
adc_slice_level_set14_0 Reset: hex:0x00; |
| [05:00] RW/V |
adc_slice_level_set14_p1 Reset: hex:0x15; |
+0x000002c8 Register(32 bit) adc_slicer_level_set15_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2c8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x002b0015 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 1 | 0 | 1 |
| Name | - | adc_slice_level_set15_m1 | - | adc_slice_level_set15_0 | - | adc_slice_level_set15_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adc_slice_level_set15_m1 Reset: hex:0x2b; |
| [13:08] RW/V |
adc_slice_level_set15_0 Reset: hex:0x00; |
| [05:00] RW/V |
adc_slice_level_set15_p1 Reset: hex:0x15; |
+0x000002cc Register(32 bit) adc_err_level_set0_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2cc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x20350b1f | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 1 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adc_err_level_set0_m3 | - | adc_err_level_set0_m1 | - | adc_err_level_set0_p1 | - | adc_err_level_set0_p3 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
adc_err_level_set0_m3 Reset: hex:0x20; |
| [21:16] RW/V |
adc_err_level_set0_m1 Reset: hex:0x35; |
| [13:08] RW/V |
adc_err_level_set0_p1 Reset: hex:0x0b; |
| [05:00] RW/V |
adc_err_level_set0_p3 Reset: hex:0x1f; |
+0x000002d0 Register(32 bit) adc_err_level_set1_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2d0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x20350b1f | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 1 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adc_err_level_set1_m3 | - | adc_err_level_set1_m1 | - | adc_err_level_set1_p1 | - | adc_err_level_set1_p3 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
adc_err_level_set1_m3 Reset: hex:0x20; |
| [21:16] RW/V |
adc_err_level_set1_m1 Reset: hex:0x35; |
| [13:08] RW/V |
adc_err_level_set1_p1 Reset: hex:0x0b; |
| [05:00] RW/V |
adc_err_level_set1_p3 Reset: hex:0x1f; |
+0x000002d4 Register(32 bit) adc_err_level_set2_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2d4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x20350b1f | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 1 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adc_err_level_set2_m3 | - | adc_err_level_set2_m1 | - | adc_err_level_set2_p1 | - | adc_err_level_set2_p3 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
adc_err_level_set2_m3 Reset: hex:0x20; |
| [21:16] RW/V |
adc_err_level_set2_m1 Reset: hex:0x35; |
| [13:08] RW/V |
adc_err_level_set2_p1 Reset: hex:0x0b; |
| [05:00] RW/V |
adc_err_level_set2_p3 Reset: hex:0x1f; |
+0x000002d8 Register(32 bit) adc_err_level_set3_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2d8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x20350b1f | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 1 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adc_err_level_set3_m3 | - | adc_err_level_set3_m1 | - | adc_err_level_set3_p1 | - | adc_err_level_set3_p3 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
adc_err_level_set3_m3 Reset: hex:0x20; |
| [21:16] RW/V |
adc_err_level_set3_m1 Reset: hex:0x35; |
| [13:08] RW/V |
adc_err_level_set3_p1 Reset: hex:0x0b; |
| [05:00] RW/V |
adc_err_level_set3_p3 Reset: hex:0x1f; |
+0x000002dc Register(32 bit) adc_err_level_set4_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2dc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x20350b1f | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 1 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adc_err_level_set4_m3 | - | adc_err_level_set4_m1 | - | adc_err_level_set4_p1 | - | adc_err_level_set4_p3 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
adc_err_level_set4_m3 Reset: hex:0x20; |
| [21:16] RW/V |
adc_err_level_set4_m1 Reset: hex:0x35; |
| [13:08] RW/V |
adc_err_level_set4_p1 Reset: hex:0x0b; |
| [05:00] RW/V |
adc_err_level_set4_p3 Reset: hex:0x1f; |
+0x000002e0 Register(32 bit) adc_err_level_set5_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2e0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x20350b1f | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 1 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adc_err_level_set5_m3 | - | adc_err_level_set5_m1 | - | adc_err_level_set5_p1 | - | adc_err_level_set5_p3 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
adc_err_level_set5_m3 Reset: hex:0x20; |
| [21:16] RW/V |
adc_err_level_set5_m1 Reset: hex:0x35; |
| [13:08] RW/V |
adc_err_level_set5_p1 Reset: hex:0x0b; |
| [05:00] RW/V |
adc_err_level_set5_p3 Reset: hex:0x1f; |
+0x000002e4 Register(32 bit) adc_err_level_set6_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2e4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x20350b1f | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 1 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adc_err_level_set6_m3 | - | adc_err_level_set6_m1 | - | adc_err_level_set6_p1 | - | adc_err_level_set6_p3 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
adc_err_level_set6_m3 Reset: hex:0x20; |
| [21:16] RW/V |
adc_err_level_set6_m1 Reset: hex:0x35; |
| [13:08] RW/V |
adc_err_level_set6_p1 Reset: hex:0x0b; |
| [05:00] RW/V |
adc_err_level_set6_p3 Reset: hex:0x1f; |
+0x000002e8 Register(32 bit) adc_err_level_set7_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2e8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x20350b1f | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 1 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adc_err_level_set7_m3 | - | adc_err_level_set7_m1 | - | adc_err_level_set7_p1 | - | adc_err_level_set7_p3 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
adc_err_level_set7_m3 Reset: hex:0x20; |
| [21:16] RW/V |
adc_err_level_set7_m1 Reset: hex:0x35; |
| [13:08] RW/V |
adc_err_level_set7_p1 Reset: hex:0x0b; |
| [05:00] RW/V |
adc_err_level_set7_p3 Reset: hex:0x1f; |
+0x000002ec Register(32 bit) adc_err_level_set8_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2ec at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x20350b1f | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 1 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adc_err_level_set8_m3 | - | adc_err_level_set8_m1 | - | adc_err_level_set8_p1 | - | adc_err_level_set8_p3 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
adc_err_level_set8_m3 Reset: hex:0x20; |
| [21:16] RW/V |
adc_err_level_set8_m1 Reset: hex:0x35; |
| [13:08] RW/V |
adc_err_level_set8_p1 Reset: hex:0x0b; |
| [05:00] RW/V |
adc_err_level_set8_p3 Reset: hex:0x1f; |
+0x000002f0 Register(32 bit) adc_err_level_set9_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2f0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x20350b1f | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 1 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adc_err_level_set9_m3 | - | adc_err_level_set9_m1 | - | adc_err_level_set9_p1 | - | adc_err_level_set9_p3 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
adc_err_level_set9_m3 Reset: hex:0x20; |
| [21:16] RW/V |
adc_err_level_set9_m1 Reset: hex:0x35; |
| [13:08] RW/V |
adc_err_level_set9_p1 Reset: hex:0x0b; |
| [05:00] RW/V |
adc_err_level_set9_p3 Reset: hex:0x1f; |
+0x000002f4 Register(32 bit) adc_err_level_set10_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2f4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x20350b1f | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 1 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adc_err_level_set10_m3 | - | adc_err_level_set10_m1 | - | adc_err_level_set10_p1 | - | adc_err_level_set10_p3 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
adc_err_level_set10_m3 Reset: hex:0x20; |
| [21:16] RW/V |
adc_err_level_set10_m1 Reset: hex:0x35; |
| [13:08] RW/V |
adc_err_level_set10_p1 Reset: hex:0x0b; |
| [05:00] RW/V |
adc_err_level_set10_p3 Reset: hex:0x1f; |
+0x000002f8 Register(32 bit) adc_err_level_set11_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2f8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x20350b1f | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 1 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adc_err_level_set11_m3 | - | adc_err_level_set11_m1 | - | adc_err_level_set11_p1 | - | adc_err_level_set11_p3 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
adc_err_level_set11_m3 Reset: hex:0x20; |
| [21:16] RW/V |
adc_err_level_set11_m1 Reset: hex:0x35; |
| [13:08] RW/V |
adc_err_level_set11_p1 Reset: hex:0x0b; |
| [05:00] RW/V |
adc_err_level_set11_p3 Reset: hex:0x1f; |
+0x000002fc Register(32 bit) adc_err_level_set12_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e2fc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x20350b1f | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 1 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adc_err_level_set12_m3 | - | adc_err_level_set12_m1 | - | adc_err_level_set12_p1 | - | adc_err_level_set12_p3 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
adc_err_level_set12_m3 Reset: hex:0x20; |
| [21:16] RW/V |
adc_err_level_set12_m1 Reset: hex:0x35; |
| [13:08] RW/V |
adc_err_level_set12_p1 Reset: hex:0x0b; |
| [05:00] RW/V |
adc_err_level_set12_p3 Reset: hex:0x1f; |
+0x00000300 Register(32 bit) adc_err_level_set13_control
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e300 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x20350b1f | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 1 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adc_err_level_set13_m3 | - | adc_err_level_set13_m1 | - | adc_err_level_set13_p1 | - | adc_err_level_set13_p3 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
adc_err_level_set13_m3 Reset: hex:0x20; |
| [21:16] RW/V |
adc_err_level_set13_m1 Reset: hex:0x35; |
| [13:08] RW/V |
adc_err_level_set13_p1 Reset: hex:0x0b; |
| [05:00] RW/V |
adc_err_level_set13_p3 Reset: hex:0x1f; |
+0x00000304 Register(32 bit) adc_err_level_set14_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e304 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x20350b1f | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 1 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adc_err_level_set14_m3 | - | adc_err_level_set14_m1 | - | adc_err_level_set14_p1 | - | adc_err_level_set14_p3 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
adc_err_level_set14_m3 Reset: hex:0x20; |
| [21:16] RW/V |
adc_err_level_set14_m1 Reset: hex:0x35; |
| [13:08] RW/V |
adc_err_level_set14_p1 Reset: hex:0x0b; |
| [05:00] RW/V |
adc_err_level_set14_p3 Reset: hex:0x1f; |
+0x00000308 Register(32 bit) adc_err_level_set15_control
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e308 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x20350b1f | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 1 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adc_err_level_set15_m3 | - | adc_err_level_set15_m1 | - | adc_err_level_set15_p1 | - | adc_err_level_set15_p3 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
adc_err_level_set15_m3 Reset: hex:0x20; |
| [21:16] RW/V |
adc_err_level_set15_m1 Reset: hex:0x35; |
| [13:08] RW/V |
adc_err_level_set15_p1 Reset: hex:0x0b; |
| [05:00] RW/V |
adc_err_level_set15_p3 Reset: hex:0x1f; |
+0x0000030c Register(32 bit) rxsararray_valid_calassist_ctrl0
Rx SAR Array Valid Calibration Assistance Control
Rx SAR Array Valid Calibration Assistance Control
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e30c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xffffffe0 | ||
| Undefined | 0xffffffe0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 |
| Name | - | rxsararrayvalidcalassist_calmeas_req | rxsararrayvalidcalassist_calmeas_timer_pow2 | |||||||||||||||||||||||||||||
| Access | - | RW | RW | |||||||||||||||||||||||||||||
| [04:04] RW |
rxsararrayvalidcalassist_calmeas_req Reset: hex:0x0; |
| [03:00] RW |
rxsararrayvalidcalassist_calmeas_timer_pow2 Reset: hex:0x0; |
+0x00000310 Register(32 bit) rxsararray_valid_calassist_ctrl1
Rx SAR Array Valid Calibration Assistance Control
Rx SAR Array Valid Calibration Assistance Control
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e310 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | rxsararrayvalidcalassist_calmeas_dat_mask_31to0 | |||||||||||||||||||||||||||||||
| Access | RW | |||||||||||||||||||||||||||||||
| [31:00] RW |
rxsararrayvalidcalassist_calmeas_dat_mask_31to0 Reset: hex:0x00000000; |
+0x00000314 Register(32 bit) rxsararray_valid_calassist_ctrl2
Rx SAR Array Valid Calibration Assistance Control
Rx SAR Array Valid Calibration Assistance Control
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e314 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | rxsararrayvalidcalassist_calmeas_dat_mask_63to32 | |||||||||||||||||||||||||||||||
| Access | RW | |||||||||||||||||||||||||||||||
| [31:00] RW |
rxsararrayvalidcalassist_calmeas_dat_mask_63to32 Reset: hex:0x00000000; |
+0x00000318 Register(32 bit) rxsararray_valid_calassist_status
Rx SAR Array Valid Calibration Assistance Status
Rx SAR Array Valid Calibration Assistance Status
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e318 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfe000000 | ||
| Undefined | 0xfe000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | rxsararrayvalidcalassist_calmeas_ack | rxsararrayvalidcalassist_calmeas_acc | |||||||||||||||||||||||||||||
| Access | - | RO/V | RO/V | |||||||||||||||||||||||||||||
| [24:24] RO/V |
rxsararrayvalidcalassist_calmeas_ack Reset: hex:0x0; |
| [23:00] RO/V |
rxsararrayvalidcalassist_calmeas_acc Reset: hex:0x000000; |
+0x0000031c Register(32 bit) rxsar_calassist_ctrl
Rx SAR Calibration Assistance Control
Rx SAR Calibration Assistance Control
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e31c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | rxsarcalassist_calmeas_req | rxsarcalassist_calmeas_clr_count | rxsarcalassist_calmeas_valid_count | rxsarcalassist_calmeas_pow2count | rxsarcalassist_calmeas_dlycount | rxsarcalassist_rxdat_slicer_bit_sel | rxsarcalassist_rxdat_slicer_sar_sel | rxsarcalassist_rxdat_slicer_quartet_sel | rxsarcalassist_rxdat_slicer_quad_sel | ||||||||||||||||||||||
| Access | - | RW | RW | RW | RW | RW | RW | RW | RW | RW | ||||||||||||||||||||||
| [29:29] RW |
rxsarcalassist_calmeas_req Reset: hex:0x0; |
| [28:25] RW |
rxsarcalassist_calmeas_clr_count Reset: hex:0x0; |
| [24:21] RW |
rxsarcalassist_calmeas_valid_count Reset: hex:0x0; |
| [20:18] RW |
rxsarcalassist_calmeas_pow2count Reset: hex:0x0; |
| [17:09] RW |
rxsarcalassist_calmeas_dlycount Reset: hex:0x000; |
| [08:06] RW |
rxsarcalassist_rxdat_slicer_bit_sel Reset: hex:0x0; |
| [05:04] RW |
rxsarcalassist_rxdat_slicer_sar_sel Reset: hex:0x0; |
| [03:02] RW |
rxsarcalassist_rxdat_slicer_quartet_sel Reset: hex:0x0; |
| [01:00] RW |
rxsarcalassist_rxdat_slicer_quad_sel Reset: hex:0x0; |
+0x00000320 Register(32 bit) rxsar_calassist_status
Rx SAR Calibration Assistance Status
Rx SAR Calibration Assistance Status
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e320 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffffffc | ||
| Undefined | 0xfffffffc | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 |
| Name | - | rxsarcalassist_calmeas_ack | rxsarcalassist_calmeasavg | |||||||||||||||||||||||||||||
| Access | - | RO/V | RO/V | |||||||||||||||||||||||||||||
| [01:01] RO/V |
rxsarcalassist_calmeas_ack Reset: hex:0x0; |
| [00:00] RO/V |
rxsarcalassist_calmeasavg Reset: hex:0x0; |
+0x000003ec Register(32 bit) main_fsm_control_6
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e3ec at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffe000c | ||
| Undefined | 0xfffe000c | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 |
| Name | - | rxeq_eyemeas_force_err | rxeq_force_fom_en | rxeq_force_fom | - | rxeq_eyemeas_done | rxeq_adaptation_done | |||||||||||||||||||||||||
| Access | - | RW | RW | RW | - | RW | RW | |||||||||||||||||||||||||
| [16:16] RW |
rxeq_eyemeas_force_err Reset: hex:0x0; |
| [15:15] RW |
rxeq_force_fom_en Reset: hex:0x0; |
| [14:04] RW |
rxeq_force_fom Reset: hex:0x000; |
| [01:01] RW |
rxeq_eyemeas_done Reset: hex:0x0; |
| [00:00] RW |
rxeq_adaptation_done Reset: hex:0x0; |
+0x000003f0 Register(32 bit) main_fsm_control_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e3f0 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffffffe | ||
| Undefined | 0xfffffffe | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 |
| Name | - | main_fsm_start | ||||||||||||||||||||||||||||||
| Access | - | RW | ||||||||||||||||||||||||||||||
| [00:00] RW |
main_fsm_start Reset: hex:0x0; |
+0x000003f4 Register(32 bit) main_fsm_status_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e3f4 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffffff0 | ||
| Undefined | 0xfffffff0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 |
| Name | - | rxeq_eyemeas_start | rxeq_eq_training_start | rxeq_adaptation_start | main_fsm_done | |||||||||||||||||||||||||||
| Access | - | RO/V | RO/V | RO/V | RO/V | |||||||||||||||||||||||||||
| [03:03] RO/V |
rxeq_eyemeas_start Reset: hex:0x0; |
| [02:02] RO/V |
rxeq_eq_training_start Reset: hex:0x0; |
| [01:01] RO/V |
rxeq_adaptation_start Reset: hex:0x0; |
| [00:00] RO/V |
main_fsm_done Reset: hex:0x0; |
+0x000003f8 Register(32 bit) main_fsm_control_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e3f8 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x04010020 | |
| Unaffected | 0xf8000000 | ||
| Undefined | 0xf8000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| Name | - | main_fsm_preload_en | main_fsm_contin_run | main_fsm_single_run | main_fsm_iter_max | main_fsm_timer_max | ||||||||||||||||||||||||||
| Access | - | RW | RW | RW | RW | RW | ||||||||||||||||||||||||||
| [26:26] RW |
main_fsm_preload_en Reset: hex:0x1; |
| [25:25] RW |
main_fsm_contin_run Reset: hex:0x0; |
| [24:24] RW |
main_fsm_single_run Reset: hex:0x0; |
| [23:08] RW |
main_fsm_iter_max Reset: hex:0x0100; |
| [07:00] RW |
main_fsm_timer_max Reset: hex:0x20; |
+0x000003fc Register(32 bit) main_fsm_control_2
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e3fc at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00000001 | ||
| Undefined | 0x00000001 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - |
| Name | main_fsm_init_edgvref_off | main_fsm_init_ffe_off | main_fsm_init_vref_off | - | ||||||||||||||||||||||||||||
| Access | RW | RW | RW | - | ||||||||||||||||||||||||||||
| [31:29] RW |
main_fsm_init_edgvref_off Reset: hex:0x0; |
| [28:05] RW |
main_fsm_init_ffe_off Reset: hex:0x000000; |
| [04:01] RW |
main_fsm_init_vref_off Reset: hex:0x0; |
+0x00000400 Register(32 bit) main_fsm_control_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e400 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00800000 | |
| Unaffected | 0xff008001 | ||
| Undefined | 0xff008001 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - |
| Name | - | main_fsm_init_update_en | main_fsm_init_cdr_ffe_off | - | main_fsm_cdr_ffe_ofc_en | main_fsm_cdr_ffe_vref_en | main_fsm_cdr_ffe_en | main_fsm_dfe_en | main_fsm_edgvref_en | main_fsm_adcofc_en | main_fsm_adcvref_en | main_fsm_affe_en | main_fsm_ofc_en | main_fsm_ops_en | main_fsm_ffe_en | main_fsm_vref_en | main_fsm_vga_en | main_fsm_init_en | - | |||||||||||||
| Access | - | RW | RW | - | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | - | |||||||||||||
| [23:23] RW |
main_fsm_init_update_en Reset: hex:0x1; |
| [22:16] RW |
main_fsm_init_cdr_ffe_off Reset: hex:0x00; |
| [14:14] RW |
main_fsm_cdr_ffe_ofc_en Reset: hex:0x0; |
| [13:13] RW |
main_fsm_cdr_ffe_vref_en Reset: hex:0x0; |
| [12:12] RW |
main_fsm_cdr_ffe_en Reset: hex:0x0; |
| [11:11] RW |
main_fsm_dfe_en Reset: hex:0x0; |
| [10:10] RW |
main_fsm_edgvref_en Reset: hex:0x0; |
| [09:09] RW |
main_fsm_adcofc_en Reset: hex:0x0; |
| [08:08] RW |
main_fsm_adcvref_en Reset: hex:0x0; |
| [07:07] RW |
main_fsm_affe_en Reset: hex:0x0; |
| [06:06] RW |
main_fsm_ofc_en Reset: hex:0x0; |
| [05:05] RW |
main_fsm_ops_en Reset: hex:0x0; |
| [04:04] RW |
main_fsm_ffe_en Reset: hex:0x0; |
| [03:03] RW |
main_fsm_vref_en Reset: hex:0x0; |
| [02:02] RW |
main_fsm_vga_en Reset: hex:0x0; |
| [01:01] RW |
main_fsm_init_en Reset: hex:0x0; |
+0x00000404 Register(32 bit) taps_set_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e404 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xffff8780 | ||
| Undefined | 0xffff8780 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | taps_set_update_dis | taps_set_init_dis | taps_set_fw_mode | taps_set_mode | - | taps_set_sel | cmod_smpl_sel | cmod | |||||||||||||||||||||||
| Access | - | RW | RW | RW | RW | - | RW | RW | RW | |||||||||||||||||||||||
| [14:14] RW |
taps_set_update_dis Reset: hex:0x0; |
| [13:13] RW |
taps_set_init_dis Reset: hex:0x0; |
| [12:12] RW |
taps_set_fw_mode Reset: hex:0x0; |
| [11:11] RW |
taps_set_mode Reset: hex:0x0; |
| [06:03] RW |
taps_set_sel Reset: hex:0x0; |
| [02:01] RW |
cmod_smpl_sel Reset: hex:0x0; |
| [00:00] RW |
cmod Reset: hex:0x0; |
+0x00000408 Register(32 bit) rx_gearbox_ctrl
Rx Gearbox Control
Rx Gearbox Control
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e408 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x73400000 | |
| Unaffected | 0x0000fffc | ||
| Undefined | 0x0000fffc | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 |
| Name | rd_ptr_max | rd_ptr_en_delay | wr_ptr_max | wr_ptr_en_delay | - | rx_gbovr_val | rx_gbovr_en | |||||||||||||||||||||||||
| Access | RW | RW | RW | RW | - | RW | RW | |||||||||||||||||||||||||
| [31:28] RW |
rd_ptr_max Reset: hex:0x7; |
| [27:24] RW |
rd_ptr_en_delay Reset: hex:0x3; |
| [23:20] RW |
wr_ptr_max Reset: hex:0x4; |
| [19:16] RW |
wr_ptr_en_delay Reset: hex:0x0; |
| [01:01] RW |
rx_gbovr_val Reset: hex:0x0; |
| [00:00] RW |
rx_gbovr_en Reset: hex:0x0; |
+0x0000040c Register(32 bit) main_fsm_control_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e40c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x00004000 | ||
| Undefined | 0x00004000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | main_fsm_init_cdr_ffe_vref_off | main_fsm_init_cdr_ffe_ofc_off | main_fsm_init_adcofc_off | main_fsm_init_dfe_off | - | main_fsm_init_ofc_off | main_fsm_init_adcvref_off | main_fsm_init_affe_off | ||||||||||||||||||||||||
| Access | RW | RW | RW | RW | - | RW | RW | RW | ||||||||||||||||||||||||
| [31:28] RW |
main_fsm_init_cdr_ffe_vref_off Reset: hex:0x0; |
| [27:22] RW |
main_fsm_init_cdr_ffe_ofc_off Reset: hex:0x00; |
| [21:16] RW |
main_fsm_init_adcofc_off Reset: hex:0x00; |
| [15:15] RW |
main_fsm_init_dfe_off Reset: hex:0x0; |
| [13:08] RW |
main_fsm_init_ofc_off Reset: hex:0x00; |
| [07:04] RW |
main_fsm_init_adcvref_off Reset: hex:0x0; |
| [03:00] RW |
main_fsm_init_affe_off Reset: hex:0x0; |
+0x00000410 Register(32 bit) main_fsm_control_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e410 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xffffff00 | ||
| Undefined | 0xffffff00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | main_fsm_init_ops_off | ||||||||||||||||||||||||||||||
| Access | - | RW | ||||||||||||||||||||||||||||||
| [07:00] RW |
main_fsm_init_ops_off Reset: hex:0x00; |
+0x00000414 Register(32 bit) vref_control_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e414 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000040 | |
| Unaffected | 0xfffff800 | ||
| Undefined | 0xfffff800 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | vref_int_iter_max | vref_int_iter_bypass | vref_hold_en | vref_pos_updn_inv_cb | vref_neg_updn_inv_cb | ||||||||||||||||||||||||||
| Access | - | RW | RW | RW | RW | RW | ||||||||||||||||||||||||||
| [10:07] RW |
vref_int_iter_max Reset: hex:0x0; |
| [06:06] RW |
vref_int_iter_bypass Reset: hex:0x1; |
| [05:02] RW |
vref_hold_en Reset: hex:0x0; |
| [01:01] RW |
vref_pos_updn_inv_cb Reset: hex:0x0; |
| [00:00] RW |
vref_neg_updn_inv_cb Reset: hex:0x0; |
+0x00000418 Register(32 bit) vref_control_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e418 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x03600240 | |
| Unaffected | 0xfc00fc00 | ||
| Undefined | 0xfc00fc00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | - | - | - | - | - | - | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | vref_init_val_1 | - | vref_init_val_0 | ||||||||||||||||||||||||||||
| Access | - | RW | - | RW | ||||||||||||||||||||||||||||
| [25:16] RW |
vref_init_val_1 Reset: hex:0x360; |
| [09:00] RW |
vref_init_val_0 Reset: hex:0x240; |
+0x0000041c Register(32 bit) vref_control_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e41c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x01c000a0 | |
| Unaffected | 0xfc00fc00 | ||
| Undefined | 0xfc00fc00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | - | - | - | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| Name | - | vref_init_val_3 | - | vref_init_val_2 | ||||||||||||||||||||||||||||
| Access | - | RW | - | RW | ||||||||||||||||||||||||||||
| [25:16] RW |
vref_init_val_3 Reset: hex:0x1c0; |
| [09:00] RW |
vref_init_val_2 Reset: hex:0x0a0; |
+0x00000420 Register(32 bit) vref_control_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e420 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00004008 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| Name | - | vref_stats_max | vref_timer_max | |||||||||||||||||||||||||||||
| Access | - | RW | RW | |||||||||||||||||||||||||||||
| [17:08] RW |
vref_stats_max Reset: hex:0x040; |
| [07:00] RW |
vref_timer_max Reset: hex:0x08; |
+0x00000424 Register(32 bit) vref_control_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e424 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x020001ff | |
| Unaffected | 0xfc00fc00 | ||
| Undefined | 0xfc00fc00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Name | - | vref_tap_min | - | vref_tap_max | ||||||||||||||||||||||||||||
| Access | - | RW | - | RW | ||||||||||||||||||||||||||||
| [25:16] RW |
vref_tap_min Reset: hex:0x200; |
| [09:00] RW |
vref_tap_max Reset: hex:0x1ff; |
+0x00000428 Register(32 bit) vref_control_6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e428 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00001021 | |
| Unaffected | 0xffec0200 | ||
| Undefined | 0xffec0200 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | - | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
| Name | - | vref_thrs_sel | - | vref_mu_fine | - | vref_mu_coarse | vref_coarse_mu_en | |||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | RW | |||||||||||||||||||||||||
| [20:20] RW |
vref_thrs_sel Reset: hex:0x0; |
| [17:10] RW |
vref_mu_fine Reset: hex:0x04; |
| [08:01] RW |
vref_mu_coarse Reset: hex:0x10; |
| [00:00] RW |
vref_coarse_mu_en Reset: hex:0x1; |
+0x00000430 Register(32 bit) vref_status_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e430 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffffff0 | ||
| Undefined | 0xfffffff0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 |
| Name | - | vref_avg_updn | ||||||||||||||||||||||||||||||
| Access | - | RO/V | ||||||||||||||||||||||||||||||
| [03:00] RO/V |
vref_avg_updn Reset: hex:0x0; |
+0x00000434 Register(32 bit) vga_control_6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e434 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xffff0000 | ||
| Undefined | 0xffff0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | vga_tap_frac | vga_tap | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [15:08] RW/V |
vga_tap_frac Reset: hex:0x00; |
| [07:00] RW/V |
vga_tap Reset: hex:0x00; |
+0x00000438 Register(32 bit) vga_control_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e438 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000800 | |
| Unaffected | 0xfff00008 | ||
| Undefined | 0xfff00008 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 |
| Name | - | vga_stats_iter_max | - | vga_single_run | vga_contin_run | vga_start | ||||||||||||||||||||||||||
| Access | - | RW | - | RW | RW | RW | ||||||||||||||||||||||||||
| [19:04] RW |
vga_stats_iter_max Reset: hex:0x0080; |
| [02:02] RW |
vga_single_run Reset: hex:0x0; |
| [01:01] RW |
vga_contin_run Reset: hex:0x0; |
| [00:00] RW |
vga_start Reset: hex:0x0; |
+0x0000043c Register(32 bit) vga_control_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e43c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0000807f | |
| Unaffected | 0xffff0000 | ||
| Undefined | 0xffff0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Name | - | vga_tap_min | vga_tap_max | |||||||||||||||||||||||||||||
| Access | - | RW | RW | |||||||||||||||||||||||||||||
| [15:08] RW |
vga_tap_min Reset: hex:0x80; |
| [07:00] RW |
vga_tap_max Reset: hex:0x7f; |
+0x00000440 Register(32 bit) vga_control_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e440 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x60004104 | |
| Unaffected | 0x80000000 | ||
| Undefined | 0x80000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| Name | - | vga_fsm_en | vga_preld_en | vga_init_en | vga_init_val | vga_mode | vga_mu_fine | vga_mu_coarse | vga_coarse_mu_en | vga_hold_en | vga_updn_inv_cb | |||||||||||||||||||||
| Access | - | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | |||||||||||||||||||||
| [30:30] RW |
vga_fsm_en Reset: hex:0x1; |
| [29:29] RW |
vga_preld_en Reset: hex:0x1; |
| [28:28] RW |
vga_init_en Reset: hex:0x0; |
| [27:20] RW |
vga_init_val Reset: hex:0x00; |
| [19:19] RW |
vga_mode Reset: hex:0x0; |
| [18:11] RW |
vga_mu_fine Reset: hex:0x08; |
| [10:03] RW |
vga_mu_coarse Reset: hex:0x20; |
| [02:02] RW |
vga_coarse_mu_en Reset: hex:0x1; |
| [01:01] RW |
vga_hold_en Reset: hex:0x0; |
| [00:00] RW |
vga_updn_inv_cb Reset: hex:0x0; |
+0x00000444 Register(32 bit) vga_control_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e444 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00004080 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | vga_timer_max | vga_stats_max | |||||||||||||||||||||||||||||
| Access | - | RW | RW | |||||||||||||||||||||||||||||
| [17:10] RW |
vga_timer_max Reset: hex:0x10; |
| [09:00] RW |
vga_stats_max Reset: hex:0x080; |
+0x00000448 Register(32 bit) vga_control_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e448 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x3c013f04 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 1 | 1 | 1 | 1 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 1 | - | - | 1 | 1 | 1 | 1 | 1 | 1 | - | - | 0 | 0 | 0 | 1 | 0 | 0 |
| Name | - | vga_limit_low_1 | - | vga_limit_low_0 | - | vga_limit_high_1 | - | vga_limit_high_0 | ||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | - | RW | ||||||||||||||||||||||||
| [29:24] RW |
vga_limit_low_1 Reset: hex:0x3c; |
| [21:16] RW |
vga_limit_low_0 Reset: hex:0x01; |
| [13:08] RW |
vga_limit_high_1 Reset: hex:0x3f; |
| [05:00] RW |
vga_limit_high_0 Reset: hex:0x04; |
+0x0000044c Register(32 bit) vga_control_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e44c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000050 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | vga_smpl_sel | vga_mask | vga_threshold | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [29:28] RW |
vga_smpl_sel Reset: hex:0x0; |
| [27:12] RW |
vga_mask Reset: hex:0x0000; |
| [11:00] RW |
vga_threshold Reset: hex:0x050; |
+0x00000450 Register(32 bit) vga_status_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e450 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffffdfe | ||
| Undefined | 0xfffffdfe | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | - | - | - | - | - | - | - | - | 0 |
| Name | - | vga_avg_updn | - | vga_done | ||||||||||||||||||||||||||||
| Access | - | RO/V | - | RO/V | ||||||||||||||||||||||||||||
| [09:09] RO/V |
vga_avg_updn Reset: hex:0x0; |
| [00:00] RO/V |
vga_done Reset: hex:0x0; |
+0x00000454 Register(32 bit) jpp_control_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e454 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000100 | |
| Unaffected | 0xfffe8080 | ||
| Undefined | 0xfffe8080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 1 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | jpp_affe_en | - | jpp_affe_gain | - | jpp_affe_offset | ||||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | ||||||||||||||||||||||||||
| [16:16] RW |
jpp_affe_en Reset: hex:0x0; |
| [14:08] RW |
jpp_affe_gain Reset: hex:0x01; |
| [06:00] RW |
jpp_affe_offset Reset: hex:0x00; |
+0x00000458 Register(32 bit) jpp_control_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e458 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000100 | |
| Unaffected | 0xfffe0000 | ||
| Undefined | 0xfffe0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | jpp_cdr_ffe_en | jpp_cdr_ffe_gain | jpp_cdr_ffe_offset | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [16:16] RW |
jpp_cdr_ffe_en Reset: hex:0x0; |
| [15:08] RW |
jpp_cdr_ffe_gain Reset: hex:0x01; |
| [07:00] RW |
jpp_cdr_ffe_offset Reset: hex:0x00; |
+0x00000460 Register(32 bit) ffe_control_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e460 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00010020 | |
| Unaffected | 0xfff80000 | ||
| Undefined | 0xfff80000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_stats_max | ffe_timer_max | ffe_updn_inv_cb | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [18:09] RW |
ffe_stats_max Reset: hex:0x080; |
| [08:01] RW |
ffe_timer_max Reset: hex:0x10; |
| [00:00] RW |
ffe_updn_inv_cb Reset: hex:0x0; |
+0x00000464 Register(32 bit) ffe_control_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e464 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_float_hold_en | ffe_static_hold_en | |||||||||||||||||||||||||||||
| Access | - | RW | RW | |||||||||||||||||||||||||||||
| [23:15] RW |
ffe_float_hold_en Reset: hex:0x000; |
| [14:00] RW |
ffe_static_hold_en Reset: hex:0x0000; |
+0x00000468 Register(32 bit) ffe_control_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e468 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00010410 | |
| Unaffected | 0xfffe0000 | ||
| Undefined | 0xfffe0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ffe_coarse_mu_en | ffe_mu_fine | ffe_mu_coarse | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [16:16] RW |
ffe_coarse_mu_en Reset: hex:0x1; |
| [15:08] RW |
ffe_mu_fine Reset: hex:0x04; |
| [07:00] RW |
ffe_mu_coarse Reset: hex:0x10; |
+0x0000046c Register(32 bit) ffe_control_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e46c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0c03f81f | |
| Unaffected | 0xf0000000 | ||
| Undefined | 0xf0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | ffe_static_tap_min_w1 | ffe_static_tap_max_w1 | ffe_static_tap_min_w0 | ffe_static_tap_max_w0 | |||||||||||||||||||||||||||
| Access | - | RW | RW | RW | RW | |||||||||||||||||||||||||||
| [27:20] RW |
ffe_static_tap_min_w1 Reset: hex:0xc0; |
| [19:12] RW |
ffe_static_tap_max_w1 Reset: hex:0x3f; |
| [11:06] RW |
ffe_static_tap_min_w0 Reset: hex:0x20; |
| [05:00] RW |
ffe_static_tap_max_w0 Reset: hex:0x1f; |
+0x00000470 Register(32 bit) ffe_control_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e470 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00008787 | |
| Unaffected | 0xffff0000 | ||
| Undefined | 0xffff0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
| Name | - | ffe_floating_tap_min | ffe_floating_tap_max | ffe_static_tap_min_w2 | ffe_static_tap_max_w2 | |||||||||||||||||||||||||||
| Access | - | RW | RW | RW | RW | |||||||||||||||||||||||||||
| [15:12] RW |
ffe_floating_tap_min Reset: hex:0x8; |
| [11:08] RW |
ffe_floating_tap_max Reset: hex:0x7; |
| [07:04] RW |
ffe_static_tap_min_w2 Reset: hex:0x8; |
| [03:00] RW |
ffe_static_tap_max_w2 Reset: hex:0x7; |
+0x00000474 Register(32 bit) ffe_control_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e474 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xffc00000 | ||
| Undefined | 0xffc00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_init_val_floating | ffe_init_val_static_w2 | ffe_init_val_static_w1 | ffe_init_val_static_w0 | |||||||||||||||||||||||||||
| Access | - | RW | RW | RW | RW | |||||||||||||||||||||||||||
| [21:18] RW |
ffe_init_val_floating Reset: hex:0x0; |
| [17:14] RW |
ffe_init_val_static_w2 Reset: hex:0x0; |
| [13:06] RW |
ffe_init_val_static_w1 Reset: hex:0x00; |
| [05:00] RW |
ffe_init_val_static_w0 Reset: hex:0x00; |
+0x0000047c Register(32 bit) ffe_status_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e47c at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ffe_avg_updn | ||||||||||||||||||||||||||||||
| Access | - | RO/V | ||||||||||||||||||||||||||||||
| [23:00] RO/V |
ffe_avg_updn Reset: hex:0x000000; |
+0x00000490 Register(32 bit) hist_control_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e490 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000fff | |
| Unaffected | 0x00018000 | ||
| Undefined | 0x00018000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Name | hist_slc_smpl_sel | hist_adc_smpl_sel | hist_timer_max | hist_stream_sel | hist_eng_start | hist_min_en | hist_min_clr | hist_max_en | hist_max_clr | hist_filter_en | - | hist_ffesmpl_sel | hist_calc_en | hist_bin_max | ||||||||||||||||||
| Access | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | - | RW | RW | RW | ||||||||||||||||||
| [31:30] RW |
hist_slc_smpl_sel Reset: hex:0x0; |
| [29:28] RW |
hist_adc_smpl_sel Reset: hex:0x0; |
| [27:24] RW |
hist_timer_max Reset: hex:0x0; |
| [23:23] RW |
hist_stream_sel Reset: hex:0x0; |
| [22:22] RW |
hist_eng_start Reset: hex:0x0; |
| [21:21] RW |
hist_min_en Reset: hex:0x0; |
| [20:20] RW |
hist_min_clr Reset: hex:0x0; |
| [19:19] RW |
hist_max_en Reset: hex:0x0; |
| [18:18] RW |
hist_max_clr Reset: hex:0x0; |
| [17:17] RW |
hist_filter_en Reset: hex:0x0; |
| [14:13] RW |
hist_ffesmpl_sel Reset: hex:0x0; |
| [12:12] RW |
hist_calc_en Reset: hex:0x0; |
| [11:00] RW |
hist_bin_max Reset: hex:0xfff; |
+0x00000494 Register(32 bit) hist_control_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e494 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | hist_ffe_smpl_sel | hist_stats_max | hist_ffe_limit_low | hist_ffe_limit_high | ||||||||||||||||||||||||||||
| Access | RW | RW | RW | RW | ||||||||||||||||||||||||||||
| [31:28] RW |
hist_ffe_smpl_sel Reset: hex:0x0; |
| [27:18] RW |
hist_stats_max Reset: hex:0x000; |
| [17:09] RW |
hist_ffe_limit_low Reset: hex:0x000; |
| [08:00] RW |
hist_ffe_limit_high Reset: hex:0x000; |
+0x00000498 Register(32 bit) hist_control_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e498 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x02010100 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 1 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | hist_limit_high_1 | - | hist_limit_low_1 | - | hist_limit_high_0 | - | hist_limit_low_0 | ||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | - | RW | ||||||||||||||||||||||||
| [29:24] RW |
hist_limit_high_1 Reset: hex:0x02; |
| [21:16] RW |
hist_limit_low_1 Reset: hex:0x01; |
| [13:08] RW |
hist_limit_high_0 Reset: hex:0x01; |
| [05:00] RW |
hist_limit_low_0 Reset: hex:0x00; |
+0x0000049c Register(32 bit) hist_control_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e49c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x04030302 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 1 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 1 | 0 |
| Name | - | hist_limit_high_3 | - | hist_limit_low_3 | - | hist_limit_high_2 | - | hist_limit_low_2 | ||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | - | RW | ||||||||||||||||||||||||
| [29:24] RW |
hist_limit_high_3 Reset: hex:0x04; |
| [21:16] RW |
hist_limit_low_3 Reset: hex:0x03; |
| [13:08] RW |
hist_limit_high_2 Reset: hex:0x03; |
| [05:00] RW |
hist_limit_low_2 Reset: hex:0x02; |
+0x000004a0 Register(32 bit) hist_control_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4a0 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x06050504 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 1 | 1 | 0 | - | - | 0 | 0 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 0 | 1 | 0 | 1 | - | - | 0 | 0 | 0 | 1 | 0 | 0 |
| Name | - | hist_limit_high_5 | - | hist_limit_low_5 | - | hist_limit_high_4 | - | hist_limit_low_4 | ||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | - | RW | ||||||||||||||||||||||||
| [29:24] RW |
hist_limit_high_5 Reset: hex:0x06; |
| [21:16] RW |
hist_limit_low_5 Reset: hex:0x05; |
| [13:08] RW |
hist_limit_high_4 Reset: hex:0x05; |
| [05:00] RW |
hist_limit_low_4 Reset: hex:0x04; |
+0x000004a4 Register(32 bit) hist_control_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4a4 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x08070706 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 1 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 1 | 1 | 1 | - | - | 0 | 0 | 0 | 1 | 1 | 1 | - | - | 0 | 0 | 0 | 1 | 1 | 0 |
| Name | - | hist_limit_high_7 | - | hist_limit_low_7 | - | hist_limit_high_6 | - | hist_limit_low_6 | ||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | - | RW | ||||||||||||||||||||||||
| [29:24] RW |
hist_limit_high_7 Reset: hex:0x08; |
| [21:16] RW |
hist_limit_low_7 Reset: hex:0x07; |
| [13:08] RW |
hist_limit_high_6 Reset: hex:0x07; |
| [05:00] RW |
hist_limit_low_6 Reset: hex:0x06; |
+0x000004a8 Register(32 bit) hist_control_6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4a8 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0a090908 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 1 | 0 | 1 | 0 | - | - | 0 | 0 | 1 | 0 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 0 | 1 | - | - | 0 | 0 | 1 | 0 | 0 | 0 |
| Name | - | hist_limit_high_9 | - | hist_limit_low_9 | - | hist_limit_high_8 | - | hist_limit_low_8 | ||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | - | RW | ||||||||||||||||||||||||
| [29:24] RW |
hist_limit_high_9 Reset: hex:0x0a; |
| [21:16] RW |
hist_limit_low_9 Reset: hex:0x09; |
| [13:08] RW |
hist_limit_high_8 Reset: hex:0x09; |
| [05:00] RW |
hist_limit_low_8 Reset: hex:0x08; |
+0x000004ac Register(32 bit) hist_control_7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4ac at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0c0b0b0a | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 1 | 1 | 0 | 0 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 1 | - | - | 0 | 0 | 1 | 0 | 1 | 0 |
| Name | - | hist_limit_high_11 | - | hist_limit_low_11 | - | hist_limit_high_10 | - | hist_limit_low_10 | ||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | - | RW | ||||||||||||||||||||||||
| [29:24] RW |
hist_limit_high_11 Reset: hex:0x0c; |
| [21:16] RW |
hist_limit_low_11 Reset: hex:0x0b; |
| [13:08] RW |
hist_limit_high_10 Reset: hex:0x0b; |
| [05:00] RW |
hist_limit_low_10 Reset: hex:0x0a; |
+0x000004b0 Register(32 bit) hist_control_8
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4b0 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0e0d0d0c | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 1 | 1 | 1 | 0 | - | - | 0 | 0 | 1 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 1 | 0 | 1 | - | - | 0 | 0 | 1 | 1 | 0 | 0 |
| Name | - | hist_limit_high_13 | - | hist_limit_low_13 | - | hist_limit_high_12 | - | hist_limit_low_12 | ||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | - | RW | ||||||||||||||||||||||||
| [29:24] RW |
hist_limit_high_13 Reset: hex:0x0e; |
| [21:16] RW |
hist_limit_low_13 Reset: hex:0x0d; |
| [13:08] RW |
hist_limit_high_12 Reset: hex:0x0d; |
| [05:00] RW |
hist_limit_low_12 Reset: hex:0x0c; |
+0x000004b4 Register(32 bit) hist_control_9
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4b4 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x100f0f0e | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 1 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 1 | 1 | 1 | 1 | - | - | 0 | 0 | 1 | 1 | 1 | 1 | - | - | 0 | 0 | 1 | 1 | 1 | 0 |
| Name | - | hist_limit_high_15 | - | hist_limit_low_15 | - | hist_limit_high_14 | - | hist_limit_low_14 | ||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | - | RW | ||||||||||||||||||||||||
| [29:24] RW |
hist_limit_high_15 Reset: hex:0x10; |
| [21:16] RW |
hist_limit_low_15 Reset: hex:0x0f; |
| [13:08] RW |
hist_limit_high_14 Reset: hex:0x0f; |
| [05:00] RW |
hist_limit_low_14 Reset: hex:0x0e; |
+0x000004b8 Register(32 bit) hist_control_10
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4b8 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | hist_min_mask | hist_max_mask | ||||||||||||||||||||||||||||||
| Access | RW | RW | ||||||||||||||||||||||||||||||
| [31:16] RW |
hist_min_mask Reset: hex:0x0000; |
| [15:00] RW |
hist_max_mask Reset: hex:0x0000; |
+0x000004bc Register(32 bit) hist_control_11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4bc at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | hist_snr_init_val | hist_snr_sf_alpha | hist_snr_iter_max | hist_snr_init_en | hist_snr_start | |||||||||||||||||||||||||||
| Access | RW | RW | RW | RW | RW | |||||||||||||||||||||||||||
| [31:21] RW |
hist_snr_init_val Reset: hex:0x000; |
| [20:18] RW |
hist_snr_sf_alpha Reset: hex:0x0; |
| [17:02] RW |
hist_snr_iter_max Reset: hex:0x0000; |
| [01:01] RW |
hist_snr_init_en Reset: hex:0x0; |
| [00:00] RW |
hist_snr_start Reset: hex:0x0; |
+0x000004c0 Register(32 bit) hist_control_12
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4c0 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | hist_snr_smpl_mask | hist_snr_prefilter_dis | hist_snr_cont_mode | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [17:02] RW |
hist_snr_smpl_mask Reset: hex:0x0000; |
| [01:01] RW |
hist_snr_prefilter_dis Reset: hex:0x0; |
| [00:00] RW |
hist_snr_cont_mode Reset: hex:0x0; |
+0x000004c4 Register(32 bit) hist_control_13
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4c4 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000400 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | hist_smpl_mask | hist_snr_stats_max | ||||||||||||||||||||||||||||||
| Access | RW | RW | ||||||||||||||||||||||||||||||
| [31:16] RW |
hist_smpl_mask Reset: hex:0x0000; |
| [15:00] RW |
hist_snr_stats_max Reset: hex:0x0400; |
+0x000004c8 Register(32 bit) hist_status_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4c8 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xffff8000 | ||
| Undefined | 0xffff8000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | hist_bin_fom | hist_eng_done | hist_snr_done | ||||||||||||||||||||||||||||
| Access | - | RO/V | RO/V | RO/V | ||||||||||||||||||||||||||||
| [14:02] RO/V |
hist_bin_fom Reset: hex:0x0000; |
| [01:01] RO/V |
hist_eng_done Reset: hex:0x0; |
| [00:00] RO/V |
hist_snr_done Reset: hex:0x0; |
+0x000004cc Register(32 bit) hist_status_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4cc at NOC.jesd__axi (Mem)
Access RO/C/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffff800 | ||
| Undefined | 0xfffff800 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | hist_snr_curr_val | ||||||||||||||||||||||||||||||
| Access | - | RO/C/V | ||||||||||||||||||||||||||||||
| [10:00] RO/C/V |
hist_snr_curr_val Reset: hex:0x000; |
+0x000004d0 Register(32 bit) hist_status_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4d0 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xf0000000 | ||
| Undefined | 0xf0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | hist_histsats | hist_ffebin | |||||||||||||||||||||||||||||
| Access | - | RO/V | RO/V | |||||||||||||||||||||||||||||
| [27:12] RO/V |
hist_histsats Reset: hex:0x0000; |
| [11:00] RO/V |
hist_ffebin Reset: hex:0x000; |
+0x000004d4 Register(32 bit) hist_status_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4d4 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | hist_bin_min_idx_3 | hist_bin_max_idx_3 | hist_bin_min_idx_2 | hist_bin_max_idx_2 | hist_bin_min_idx_1 | hist_bin_max_idx_1 | hist_bin_min_idx_0 | hist_bin_max_idx_0 | ||||||||||||||||||||||||
| Access | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | ||||||||||||||||||||||||
| [31:28] RO/V |
hist_bin_min_idx_3 Reset: hex:0x0; |
| [27:24] RO/V |
hist_bin_max_idx_3 Reset: hex:0x0; |
| [23:20] RO/V |
hist_bin_min_idx_2 Reset: hex:0x0; |
| [19:16] RO/V |
hist_bin_max_idx_2 Reset: hex:0x0; |
| [15:12] RO/V |
hist_bin_min_idx_1 Reset: hex:0x0; |
| [11:08] RO/V |
hist_bin_max_idx_1 Reset: hex:0x0; |
| [07:04] RO/V |
hist_bin_min_idx_0 Reset: hex:0x0; |
| [03:00] RO/V |
hist_bin_max_idx_0 Reset: hex:0x0; |
+0x000004d8 Register(32 bit) hist_status_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4d8 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xf000f000 | ||
| Undefined | 0xf000f000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | hist_bin_max_val_1 | - | hist_bin_max_val_0 | ||||||||||||||||||||||||||||
| Access | - | RO/V | - | RO/V | ||||||||||||||||||||||||||||
| [27:16] RO/V |
hist_bin_max_val_1 Reset: hex:0x000; |
| [11:00] RO/V |
hist_bin_max_val_0 Reset: hex:0x000; |
+0x000004e0 Register(32 bit) hist_status_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4e0 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xf000f000 | ||
| Undefined | 0xf000f000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | hist_bin_max_val_3 | - | hist_bin_max_val_2 | ||||||||||||||||||||||||||||
| Access | - | RO/V | - | RO/V | ||||||||||||||||||||||||||||
| [27:16] RO/V |
hist_bin_max_val_3 Reset: hex:0x000; |
| [11:00] RO/V |
hist_bin_max_val_2 Reset: hex:0x000; |
+0x000004e4 Register(32 bit) hist_status_6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4e4 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xf000f000 | ||
| Undefined | 0xf000f000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | hist_bin_min_val_1 | - | hist_bin_min_val_0 | ||||||||||||||||||||||||||||
| Access | - | RO/V | - | RO/V | ||||||||||||||||||||||||||||
| [27:16] RO/V |
hist_bin_min_val_1 Reset: hex:0x000; |
| [11:00] RO/V |
hist_bin_min_val_0 Reset: hex:0x000; |
+0x000004e8 Register(32 bit) hist_status_7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4e8 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xf000f000 | ||
| Undefined | 0xf000f000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | hist_bin_min_val_3 | - | hist_bin_min_val_2 | ||||||||||||||||||||||||||||
| Access | - | RO/V | - | RO/V | ||||||||||||||||||||||||||||
| [27:16] RO/V |
hist_bin_min_val_3 Reset: hex:0x000; |
| [11:00] RO/V |
hist_bin_min_val_2 Reset: hex:0x000; |
+0x000004ec Register(32 bit) hist_status_8
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4ec at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xf000f000 | ||
| Undefined | 0xf000f000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | hist_bin_cntr_1 | - | hist_bin_cntr_0 | ||||||||||||||||||||||||||||
| Access | - | RO/V | - | RO/V | ||||||||||||||||||||||||||||
| [27:16] RO/V |
hist_bin_cntr_1 Reset: hex:0x000; |
| [11:00] RO/V |
hist_bin_cntr_0 Reset: hex:0x000; |
+0x000004f0 Register(32 bit) hist_status_9
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4f0 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xf000f000 | ||
| Undefined | 0xf000f000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | hist_bin_cntr_3 | - | hist_bin_cntr_2 | ||||||||||||||||||||||||||||
| Access | - | RO/V | - | RO/V | ||||||||||||||||||||||||||||
| [27:16] RO/V |
hist_bin_cntr_3 Reset: hex:0x000; |
| [11:00] RO/V |
hist_bin_cntr_2 Reset: hex:0x000; |
+0x000004f4 Register(32 bit) hist_status_10
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4f4 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xf000f000 | ||
| Undefined | 0xf000f000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | hist_bin_cntr_5 | - | hist_bin_cntr_4 | ||||||||||||||||||||||||||||
| Access | - | RO/V | - | RO/V | ||||||||||||||||||||||||||||
| [27:16] RO/V |
hist_bin_cntr_5 Reset: hex:0x000; |
| [11:00] RO/V |
hist_bin_cntr_4 Reset: hex:0x000; |
+0x000004f8 Register(32 bit) hist_status_11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4f8 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xf000f000 | ||
| Undefined | 0xf000f000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | hist_bin_cntr_7 | - | hist_bin_cntr_6 | ||||||||||||||||||||||||||||
| Access | - | RO/V | - | RO/V | ||||||||||||||||||||||||||||
| [27:16] RO/V |
hist_bin_cntr_7 Reset: hex:0x000; |
| [11:00] RO/V |
hist_bin_cntr_6 Reset: hex:0x000; |
+0x000004fc Register(32 bit) hist_status_12
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e4fc at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xf000f000 | ||
| Undefined | 0xf000f000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | hist_bin_cntr_9 | - | hist_bin_cntr_8 | ||||||||||||||||||||||||||||
| Access | - | RO/V | - | RO/V | ||||||||||||||||||||||||||||
| [27:16] RO/V |
hist_bin_cntr_9 Reset: hex:0x000; |
| [11:00] RO/V |
hist_bin_cntr_8 Reset: hex:0x000; |
+0x00000500 Register(32 bit) hist_status_13
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e500 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xf000f000 | ||
| Undefined | 0xf000f000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | hist_bin_cntr_11 | - | hist_bin_cntr_10 | ||||||||||||||||||||||||||||
| Access | - | RO/V | - | RO/V | ||||||||||||||||||||||||||||
| [27:16] RO/V |
hist_bin_cntr_11 Reset: hex:0x000; |
| [11:00] RO/V |
hist_bin_cntr_10 Reset: hex:0x000; |
+0x00000510 Register(32 bit) hist_status_14
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e510 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xf000f000 | ||
| Undefined | 0xf000f000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | hist_bin_cntr_13 | - | hist_bin_cntr_12 | ||||||||||||||||||||||||||||
| Access | - | RO/V | - | RO/V | ||||||||||||||||||||||||||||
| [27:16] RO/V |
hist_bin_cntr_13 Reset: hex:0x000; |
| [11:00] RO/V |
hist_bin_cntr_12 Reset: hex:0x000; |
+0x00000514 Register(32 bit) hist_status_15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e514 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xf000f000 | ||
| Undefined | 0xf000f000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | hist_bin_cntr_15 | - | hist_bin_cntr_14 | ||||||||||||||||||||||||||||
| Access | - | RO/V | - | RO/V | ||||||||||||||||||||||||||||
| [27:16] RO/V |
hist_bin_cntr_15 Reset: hex:0x000; |
| [11:00] RO/V |
hist_bin_cntr_14 Reset: hex:0x000; |
+0x00000518 Register(32 bit) ops_control_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e518 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000411 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
| Name | ops_grp_sel_fw_mode | ops_grp_sel | ops_bit_sel_load_en | ops_bit_sel_load | ops_bit_sel_fw_mode | ops_bit_sel | ops_updn_inv_cb | ops_bit_inv_cb | ops_hold_en | ops_mu_fine | ops_mu_coarse | ops_coarse_mu_en | ||||||||||||||||||||
| Access | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | ||||||||||||||||||||
| [31:31] RW |
ops_grp_sel_fw_mode Reset: hex:0x0; |
| [30:28] RW |
ops_grp_sel Reset: hex:0x0; |
| [27:27] RW |
ops_bit_sel_load_en Reset: hex:0x0; |
| [26:24] RW |
ops_bit_sel_load Reset: hex:0x0; |
| [23:23] RW |
ops_bit_sel_fw_mode Reset: hex:0x0; |
| [22:20] RW |
ops_bit_sel Reset: hex:0x0; |
| [19:19] RW |
ops_updn_inv_cb Reset: hex:0x0; |
| [18:18] RW |
ops_bit_inv_cb Reset: hex:0x0; |
| [17:17] RW |
ops_hold_en Reset: hex:0x0; |
| [16:09] RW |
ops_mu_fine Reset: hex:0x02; |
| [08:01] RW |
ops_mu_coarse Reset: hex:0x08; |
| [00:00] RW |
ops_coarse_mu_en Reset: hex:0x1; |
+0x0000051c Register(32 bit) ops_control_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e51c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00002080 | |
| Unaffected | 0xf0c00000 | ||
| Undefined | 0xf0c00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ops_grp_sel_load_en | ops_grp_sel_load | - | ops_init_val | ops_timer_max | ops_stats_max | |||||||||||||||||||||||||
| Access | - | RW | RW | - | RW | RW | RW | |||||||||||||||||||||||||
| [27:27] RW |
ops_grp_sel_load_en Reset: hex:0x0; |
| [26:24] RW |
ops_grp_sel_load Reset: hex:0x0; |
| [21:14] RW |
ops_init_val Reset: hex:0x00; |
| [13:10] RW |
ops_timer_max Reset: hex:0x8; |
| [09:00] RW |
ops_stats_max Reset: hex:0x080; |
+0x00000520 Register(32 bit) ops_control_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e520 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0000807f | |
| Unaffected | 0xffc00000 | ||
| Undefined | 0xffc00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Name | - | dbg_ops_sel | ops_tap_min | ops_tap_max | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [21:16] RW |
dbg_ops_sel Reset: hex:0x00; |
| [15:08] RW |
ops_tap_min Reset: hex:0x80; |
| [07:00] RW |
ops_tap_max Reset: hex:0x7f; |
+0x00000524 Register(32 bit) ops_control_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e524 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xffffff00 | ||
| Undefined | 0xffffff00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ops_lms_mask | ||||||||||||||||||||||||||||||
| Access | - | RW | ||||||||||||||||||||||||||||||
| [07:00] RW |
ops_lms_mask Reset: hex:0x00; |
+0x0000052c Register(32 bit) ops_status_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e52c at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xffffff00 | ||
| Undefined | 0xffffff00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ops_updn | ||||||||||||||||||||||||||||||
| Access | - | RO/V | ||||||||||||||||||||||||||||||
| [07:00] RO/V |
ops_updn Reset: hex:0x00; |
+0x00000534 Register(32 bit) ops_status_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e534 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xffffff00 | ||
| Undefined | 0xffffff00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | dbg_ops_mux | ||||||||||||||||||||||||||||||
| Access | - | RO/V | ||||||||||||||||||||||||||||||
| [07:00] RO/V |
dbg_ops_mux Reset: hex:0x00; |
+0x00000538 Register(32 bit) adcvref_control_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e538 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000040 | |
| Unaffected | 0xfffff800 | ||
| Undefined | 0xfffff800 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | adcvref_int_iter_max | adcvref_int_iter_bypass | adcvref_hold_en | adcvref_pos_updn_inv_cb | adcvref_neg_updn_inv_cb | ||||||||||||||||||||||||||
| Access | - | RW | RW | RW | RW | RW | ||||||||||||||||||||||||||
| [10:07] RW |
adcvref_int_iter_max Reset: hex:0x0; |
| [06:06] RW |
adcvref_int_iter_bypass Reset: hex:0x1; |
| [05:02] RW |
adcvref_hold_en Reset: hex:0x0; |
| [01:01] RW |
adcvref_pos_updn_inv_cb Reset: hex:0x0; |
| [00:00] RW |
adcvref_neg_updn_inv_cb Reset: hex:0x0; |
+0x0000053c Register(32 bit) adcvref_control_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e53c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00003624 | |
| Unaffected | 0xffffc0c0 | ||
| Undefined | 0xffffc0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 1 | 0 | 1 | 1 | 0 | - | - | 1 | 0 | 0 | 1 | 0 | 0 |
| Name | - | adcvref_init_val_1 | - | adcvref_init_val_0 | ||||||||||||||||||||||||||||
| Access | - | RW | - | RW | ||||||||||||||||||||||||||||
| [13:08] RW |
adcvref_init_val_1 Reset: hex:0x36; |
| [05:00] RW |
adcvref_init_val_0 Reset: hex:0x24; |
+0x00000540 Register(32 bit) adcvref_control_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e540 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00001c0a | |
| Unaffected | 0xffffc0c0 | ||
| Undefined | 0xffffc0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 0 | 0 | - | - | 0 | 0 | 1 | 0 | 1 | 0 |
| Name | - | adcvref_init_val_3 | - | adcvref_init_val_2 | ||||||||||||||||||||||||||||
| Access | - | RW | - | RW | ||||||||||||||||||||||||||||
| [13:08] RW |
adcvref_init_val_3 Reset: hex:0x1c; |
| [05:00] RW |
adcvref_init_val_2 Reset: hex:0x0a; |
+0x00000544 Register(32 bit) adcvref_control_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e544 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00004008 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| Name | - | adcvref_stats_max | adcvref_timer_max | |||||||||||||||||||||||||||||
| Access | - | RW | RW | |||||||||||||||||||||||||||||
| [17:08] RW |
adcvref_stats_max Reset: hex:0x040; |
| [07:00] RW |
adcvref_timer_max Reset: hex:0x08; |
+0x00000548 Register(32 bit) adcvref_control_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e548 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0000201f | |
| Unaffected | 0xffffc0c0 | ||
| Undefined | 0xffffc0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adcvref_tap_min | - | adcvref_tap_max | ||||||||||||||||||||||||||||
| Access | - | RW | - | RW | ||||||||||||||||||||||||||||
| [13:08] RW |
adcvref_tap_min Reset: hex:0x20; |
| [05:00] RW |
adcvref_tap_max Reset: hex:0x1f; |
+0x0000054c Register(32 bit) adcvref_control_6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e54c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000811 | |
| Unaffected | 0xffec0200 | ||
| Undefined | 0xffec0200 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | - | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
| Name | - | adcvref_thrs_sel | - | adcvref_mu_fine | - | adcvref_mu_coarse | adcvref_coarse_mu_en | |||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | RW | |||||||||||||||||||||||||
| [20:20] RW |
adcvref_thrs_sel Reset: hex:0x0; |
| [17:10] RW |
adcvref_mu_fine Reset: hex:0x02; |
| [08:01] RW |
adcvref_mu_coarse Reset: hex:0x08; |
| [00:00] RW |
adcvref_coarse_mu_en Reset: hex:0x1; |
+0x00000550 Register(32 bit) adcvref_status_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e550 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffffff0 | ||
| Undefined | 0xfffffff0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 |
| Name | - | adcvref_avg_updn | ||||||||||||||||||||||||||||||
| Access | - | RO/V | ||||||||||||||||||||||||||||||
| [03:00] RO/V |
adcvref_avg_updn Reset: hex:0x0; |
+0x00000560 Register(32 bit) affe_control_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e560 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00010020 | |
| Unaffected | 0xfff80000 | ||
| Undefined | 0xfff80000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_stats_max | affe_timer_max | affe_updn_inv_cb | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [18:09] RW |
affe_stats_max Reset: hex:0x080; |
| [08:01] RW |
affe_timer_max Reset: hex:0x10; |
| [00:00] RW |
affe_updn_inv_cb Reset: hex:0x0; |
+0x00000564 Register(32 bit) affe_control_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e564 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00016000 | |
| Unaffected | 0xe0000800 | ||
| Undefined | 0xe0000800 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_tap_dis_value | affe_tap_force_dis | affe_taps_if_dis | affe_taps_if_dis_hold_thr | - | affe_init_val | affe_hold_en | ||||||||||||||||||||||||
| Access | - | RW | RW | RW | RW | - | RW | RW | ||||||||||||||||||||||||
| [28:22] RW |
affe_tap_dis_value Reset: hex:0x00; |
| [21:18] RW |
affe_tap_force_dis Reset: hex:0x0; |
| [17:17] RW |
affe_taps_if_dis Reset: hex:0x0; |
| [16:12] RW |
affe_taps_if_dis_hold_thr Reset: hex:0x16; |
| [10:04] RW |
affe_init_val Reset: hex:0x00; |
| [03:00] RW |
affe_hold_en Reset: hex:0x0; |
+0x00000568 Register(32 bit) affe_control_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e568 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00010410 | |
| Unaffected | 0xfffe0000 | ||
| Undefined | 0xfffe0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | affe_coarse_mu_en | affe_mu_fine | affe_mu_coarse | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [16:16] RW |
affe_coarse_mu_en Reset: hex:0x1; |
| [15:08] RW |
affe_mu_fine Reset: hex:0x04; |
| [07:00] RW |
affe_mu_coarse Reset: hex:0x10; |
+0x0000056c Register(32 bit) affe_control_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e56c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0000403f | |
| Unaffected | 0xffff8080 | ||
| Undefined | 0xffff8080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
| Name | - | affe_tap_min | - | affe_tap_max | ||||||||||||||||||||||||||||
| Access | - | RW | - | RW | ||||||||||||||||||||||||||||
| [14:08] RW |
affe_tap_min Reset: hex:0x40; |
| [06:00] RW |
affe_tap_max Reset: hex:0x3f; |
+0x00000570 Register(32 bit) affe_status_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e570 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffffff0 | ||
| Undefined | 0xfffffff0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 |
| Name | - | affe_avg_updn | ||||||||||||||||||||||||||||||
| Access | - | RO/V | ||||||||||||||||||||||||||||||
| [03:00] RO/V |
affe_avg_updn Reset: hex:0x0; |
+0x0000057c Register(32 bit) ofc_control_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e57c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00010020 | |
| Unaffected | 0xf0380000 | ||
| Undefined | 0xf0380000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ofc_hold_en | - | ofc_stats_max | ofc_timer_max | ofc_updn_inv_cb | ||||||||||||||||||||||||||
| Access | - | RW | - | RW | RW | RW | ||||||||||||||||||||||||||
| [27:22] RW |
ofc_hold_en Reset: hex:0x00; |
| [18:09] RW |
ofc_stats_max Reset: hex:0x080; |
| [08:01] RW |
ofc_timer_max Reset: hex:0x10; |
| [00:00] RW |
ofc_updn_inv_cb Reset: hex:0x0; |
+0x00000580 Register(32 bit) ofc_control_1a
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e580 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000b42d0 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ofc_init_val_2 | ofc_init_val_1 | ofc_init_val_0 | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [29:20] RW |
ofc_init_val_2 Reset: hex:0x000; |
| [19:10] RW |
ofc_init_val_1 Reset: hex:0x2d0; |
| [09:00] RW |
ofc_init_val_0 Reset: hex:0x2d0; |
+0x00000584 Register(32 bit) ofc_control_1b
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e584 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x1304c000 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ofc_init_val_5 | ofc_init_val_4 | ofc_init_val_3 | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [29:20] RW |
ofc_init_val_5 Reset: hex:0x130; |
| [19:10] RW |
ofc_init_val_4 Reset: hex:0x130; |
| [09:00] RW |
ofc_init_val_3 Reset: hex:0x000; |
+0x00000588 Register(32 bit) ofc_control_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e588 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00010410 | |
| Unaffected | 0xfffe0000 | ||
| Undefined | 0xfffe0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ofc_coarse_mu_en | ofc_mu_fine | ofc_mu_coarse | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [16:16] RW |
ofc_coarse_mu_en Reset: hex:0x1; |
| [15:08] RW |
ofc_mu_fine Reset: hex:0x04; |
| [07:00] RW |
ofc_mu_coarse Reset: hex:0x10; |
+0x0000058c Register(32 bit) ofc_control_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e58c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000801ff | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Name | - | ofc_tap_min | ofc_tap_max | |||||||||||||||||||||||||||||
| Access | - | RW | RW | |||||||||||||||||||||||||||||
| [19:10] RW |
ofc_tap_min Reset: hex:0x200; |
| [09:00] RW |
ofc_tap_max Reset: hex:0x1ff; |
+0x00000590 Register(32 bit) ofc_status_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e590 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000ac150 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ofc_tap_zr | ofc_tap_lo | ofc_tap_hi | ||||||||||||||||||||||||||||
| Access | - | RO/V | RO/V | RO/V | ||||||||||||||||||||||||||||
| [29:20] RO/V |
ofc_tap_zr Reset: hex:0x000; |
| [19:10] RO/V |
ofc_tap_lo Reset: hex:0x2b0; |
| [09:00] RO/V |
ofc_tap_hi Reset: hex:0x150; |
+0x00000594 Register(32 bit) ffe_coeff_set0_frac_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e594 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set0_frac_post1 | ffe_coeff_set0_frac_pre1 | ffe_coeff_set0_frac_pre2 | ffe_coeff_set0_frac_pre3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set0_frac_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set0_frac_pre1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set0_frac_pre2 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set0_frac_pre3 Reset: hex:0x00; |
+0x00000598 Register(32 bit) ffe_coeff_set0_frac_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e598 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set0_frac_post5 | ffe_coeff_set0_frac_post4 | ffe_coeff_set0_frac_post3 | ffe_coeff_set0_frac_post2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set0_frac_post5 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set0_frac_post4 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set0_frac_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set0_frac_post2 Reset: hex:0x00; |
+0x0000059c Register(32 bit) ffe_coeff_set0_frac_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e59c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set0_frac_post9 | ffe_coeff_set0_frac_post8 | ffe_coeff_set0_frac_post7 | ffe_coeff_set0_frac_post6 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set0_frac_post9 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set0_frac_post8 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set0_frac_post7 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set0_frac_post6 Reset: hex:0x00; |
+0x000005a0 Register(32 bit) ffe_coeff_set0_frac_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5a0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set0_frac_bankA_float1 | ffe_coeff_set0_frac_post12 | ffe_coeff_set0_frac_post11 | ffe_coeff_set0_frac_post10 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set0_frac_bankA_float1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set0_frac_post12 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set0_frac_post11 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set0_frac_post10 Reset: hex:0x00; |
+0x000005a4 Register(32 bit) ffe_coeff_set0_frac_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5a4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set0_frac_bankB_float2 | ffe_coeff_set0_frac_bankB_float1 | ffe_coeff_set0_frac_bankA_float3 | ffe_coeff_set0_frac_bankA_float2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set0_frac_bankB_float2 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set0_frac_bankB_float1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set0_frac_bankA_float3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set0_frac_bankA_float2 Reset: hex:0x00; |
+0x000005a8 Register(32 bit) ffe_coeff_set0_frac_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5a8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set0_frac_bankC_float3 | ffe_coeff_set0_frac_bankC_float2 | ffe_coeff_set0_frac_bankC_float1 | ffe_coeff_set0_frac_bankB_float3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set0_frac_bankC_float3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set0_frac_bankC_float2 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set0_frac_bankC_float1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set0_frac_bankB_float3 Reset: hex:0x00; |
+0x000005ac Register(32 bit) ffe_coeff_set1_frac_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5ac at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set1_frac_post1 | ffe_coeff_set1_frac_pre1 | ffe_coeff_set1_frac_pre2 | ffe_coeff_set1_frac_pre3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set1_frac_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set1_frac_pre1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set1_frac_pre2 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set1_frac_pre3 Reset: hex:0x00; |
+0x000005b0 Register(32 bit) ffe_coeff_set1_frac_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5b0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set1_frac_post5 | ffe_coeff_set1_frac_post4 | ffe_coeff_set1_frac_post3 | ffe_coeff_set1_frac_post2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set1_frac_post5 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set1_frac_post4 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set1_frac_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set1_frac_post2 Reset: hex:0x00; |
+0x000005b4 Register(32 bit) ffe_coeff_set1_frac_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5b4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set1_frac_post9 | ffe_coeff_set1_frac_post8 | ffe_coeff_set1_frac_post7 | ffe_coeff_set1_frac_post6 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set1_frac_post9 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set1_frac_post8 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set1_frac_post7 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set1_frac_post6 Reset: hex:0x00; |
+0x000005b8 Register(32 bit) ffe_coeff_set1_frac_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5b8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set1_frac_bankA_float1 | ffe_coeff_set1_frac_post12 | ffe_coeff_set1_frac_post11 | ffe_coeff_set1_frac_post10 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set1_frac_bankA_float1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set1_frac_post12 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set1_frac_post11 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set1_frac_post10 Reset: hex:0x00; |
+0x000005bc Register(32 bit) ffe_coeff_set1_frac_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5bc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set1_frac_bankB_float2 | ffe_coeff_set1_frac_bankB_float1 | ffe_coeff_set1_frac_bankA_float3 | ffe_coeff_set1_frac_bankA_float2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set1_frac_bankB_float2 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set1_frac_bankB_float1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set1_frac_bankA_float3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set1_frac_bankA_float2 Reset: hex:0x00; |
+0x000005c0 Register(32 bit) ffe_coeff_set1_frac_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5c0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set1_frac_bankC_float3 | ffe_coeff_set1_frac_bankC_float2 | ffe_coeff_set1_frac_bankC_float1 | ffe_coeff_set1_frac_bankB_float3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set1_frac_bankC_float3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set1_frac_bankC_float2 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set1_frac_bankC_float1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set1_frac_bankB_float3 Reset: hex:0x00; |
+0x000005c4 Register(32 bit) ffe_coeff_set2_frac_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5c4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set2_frac_post1 | ffe_coeff_set2_frac_pre1 | ffe_coeff_set2_frac_pre2 | ffe_coeff_set2_frac_pre3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set2_frac_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set2_frac_pre1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set2_frac_pre2 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set2_frac_pre3 Reset: hex:0x00; |
+0x000005c8 Register(32 bit) ffe_coeff_set2_frac_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5c8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set2_frac_post5 | ffe_coeff_set2_frac_post4 | ffe_coeff_set2_frac_post3 | ffe_coeff_set2_frac_post2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set2_frac_post5 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set2_frac_post4 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set2_frac_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set2_frac_post2 Reset: hex:0x00; |
+0x000005cc Register(32 bit) ffe_coeff_set2_frac_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5cc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set2_frac_post9 | ffe_coeff_set2_frac_post8 | ffe_coeff_set2_frac_post7 | ffe_coeff_set2_frac_post6 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set2_frac_post9 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set2_frac_post8 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set2_frac_post7 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set2_frac_post6 Reset: hex:0x00; |
+0x000005d0 Register(32 bit) ffe_coeff_set2_frac_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5d0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set2_frac_bankA_float1 | ffe_coeff_set2_frac_post12 | ffe_coeff_set2_frac_post11 | ffe_coeff_set2_frac_post10 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set2_frac_bankA_float1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set2_frac_post12 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set2_frac_post11 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set2_frac_post10 Reset: hex:0x00; |
+0x000005d4 Register(32 bit) ffe_coeff_set2_frac_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5d4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set2_frac_bankB_float2 | ffe_coeff_set2_frac_bankB_float1 | ffe_coeff_set2_frac_bankA_float3 | ffe_coeff_set2_frac_bankA_float2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set2_frac_bankB_float2 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set2_frac_bankB_float1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set2_frac_bankA_float3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set2_frac_bankA_float2 Reset: hex:0x00; |
+0x000005d8 Register(32 bit) ffe_coeff_set2_frac_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5d8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set2_frac_bankC_float3 | ffe_coeff_set2_frac_bankC_float2 | ffe_coeff_set2_frac_bankC_float1 | ffe_coeff_set2_frac_bankB_float3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set2_frac_bankC_float3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set2_frac_bankC_float2 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set2_frac_bankC_float1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set2_frac_bankB_float3 Reset: hex:0x00; |
+0x000005dc Register(32 bit) ffe_coeff_set3_frac_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5dc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set3_frac_post1 | ffe_coeff_set3_frac_pre1 | ffe_coeff_set3_frac_pre2 | ffe_coeff_set3_frac_pre3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set3_frac_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set3_frac_pre1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set3_frac_pre2 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set3_frac_pre3 Reset: hex:0x00; |
+0x000005e0 Register(32 bit) ffe_coeff_set3_frac_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5e0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set3_frac_post5 | ffe_coeff_set3_frac_post4 | ffe_coeff_set3_frac_post3 | ffe_coeff_set3_frac_post2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set3_frac_post5 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set3_frac_post4 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set3_frac_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set3_frac_post2 Reset: hex:0x00; |
+0x000005e4 Register(32 bit) ffe_coeff_set3_frac_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5e4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set3_frac_post9 | ffe_coeff_set3_frac_post8 | ffe_coeff_set3_frac_post7 | ffe_coeff_set3_frac_post6 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set3_frac_post9 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set3_frac_post8 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set3_frac_post7 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set3_frac_post6 Reset: hex:0x00; |
+0x000005e8 Register(32 bit) ffe_coeff_set3_frac_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5e8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set3_frac_bankA_float1 | ffe_coeff_set3_frac_post12 | ffe_coeff_set3_frac_post11 | ffe_coeff_set3_frac_post10 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set3_frac_bankA_float1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set3_frac_post12 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set3_frac_post11 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set3_frac_post10 Reset: hex:0x00; |
+0x000005ec Register(32 bit) ffe_coeff_set3_frac_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5ec at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set3_frac_bankB_float2 | ffe_coeff_set3_frac_bankB_float1 | ffe_coeff_set3_frac_bankA_float3 | ffe_coeff_set3_frac_bankA_float2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set3_frac_bankB_float2 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set3_frac_bankB_float1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set3_frac_bankA_float3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set3_frac_bankA_float2 Reset: hex:0x00; |
+0x000005f0 Register(32 bit) ffe_coeff_set3_frac_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5f0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set3_frac_bankC_float3 | ffe_coeff_set3_frac_bankC_float2 | ffe_coeff_set3_frac_bankC_float1 | ffe_coeff_set3_frac_bankB_float3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set3_frac_bankC_float3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set3_frac_bankC_float2 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set3_frac_bankC_float1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set3_frac_bankB_float3 Reset: hex:0x00; |
+0x000005f4 Register(32 bit) ffe_coeff_set4_frac_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5f4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set4_frac_post1 | ffe_coeff_set4_frac_pre1 | ffe_coeff_set4_frac_pre2 | ffe_coeff_set4_frac_pre3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set4_frac_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set4_frac_pre1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set4_frac_pre2 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set4_frac_pre3 Reset: hex:0x00; |
+0x000005f8 Register(32 bit) ffe_coeff_set4_frac_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5f8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set4_frac_post5 | ffe_coeff_set4_frac_post4 | ffe_coeff_set4_frac_post3 | ffe_coeff_set4_frac_post2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set4_frac_post5 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set4_frac_post4 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set4_frac_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set4_frac_post2 Reset: hex:0x00; |
+0x000005fc Register(32 bit) ffe_coeff_set4_frac_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e5fc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set4_frac_post9 | ffe_coeff_set4_frac_post8 | ffe_coeff_set4_frac_post7 | ffe_coeff_set4_frac_post6 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set4_frac_post9 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set4_frac_post8 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set4_frac_post7 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set4_frac_post6 Reset: hex:0x00; |
+0x00000600 Register(32 bit) ffe_coeff_set4_frac_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e600 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set4_frac_bankA_float1 | ffe_coeff_set4_frac_post12 | ffe_coeff_set4_frac_post11 | ffe_coeff_set4_frac_post10 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set4_frac_bankA_float1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set4_frac_post12 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set4_frac_post11 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set4_frac_post10 Reset: hex:0x00; |
+0x00000604 Register(32 bit) ffe_coeff_set4_frac_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e604 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set4_frac_bankB_float2 | ffe_coeff_set4_frac_bankB_float1 | ffe_coeff_set4_frac_bankA_float3 | ffe_coeff_set4_frac_bankA_float2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set4_frac_bankB_float2 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set4_frac_bankB_float1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set4_frac_bankA_float3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set4_frac_bankA_float2 Reset: hex:0x00; |
+0x00000608 Register(32 bit) ffe_coeff_set4_frac_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e608 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set4_frac_bankC_float3 | ffe_coeff_set4_frac_bankC_float2 | ffe_coeff_set4_frac_bankC_float1 | ffe_coeff_set4_frac_bankB_float3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set4_frac_bankC_float3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set4_frac_bankC_float2 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set4_frac_bankC_float1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set4_frac_bankB_float3 Reset: hex:0x00; |
+0x0000060c Register(32 bit) ffe_coeff_set5_frac_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e60c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set5_frac_post1 | ffe_coeff_set5_frac_pre1 | ffe_coeff_set5_frac_pre2 | ffe_coeff_set5_frac_pre3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set5_frac_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set5_frac_pre1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set5_frac_pre2 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set5_frac_pre3 Reset: hex:0x00; |
+0x00000610 Register(32 bit) ffe_coeff_set5_frac_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e610 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set5_frac_post5 | ffe_coeff_set5_frac_post4 | ffe_coeff_set5_frac_post3 | ffe_coeff_set5_frac_post2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set5_frac_post5 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set5_frac_post4 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set5_frac_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set5_frac_post2 Reset: hex:0x00; |
+0x00000614 Register(32 bit) ffe_coeff_set5_frac_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e614 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set5_frac_post9 | ffe_coeff_set5_frac_post8 | ffe_coeff_set5_frac_post7 | ffe_coeff_set5_frac_post6 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set5_frac_post9 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set5_frac_post8 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set5_frac_post7 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set5_frac_post6 Reset: hex:0x00; |
+0x00000618 Register(32 bit) ffe_coeff_set5_frac_3
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e618 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set5_frac_bankA_float1 | ffe_coeff_set5_frac_post12 | ffe_coeff_set5_frac_post11 | ffe_coeff_set5_frac_post10 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set5_frac_bankA_float1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set5_frac_post12 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set5_frac_post11 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set5_frac_post10 Reset: hex:0x00; |
+0x0000061c Register(32 bit) ffe_coeff_set5_frac_4
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e61c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set5_frac_bankB_float2 | ffe_coeff_set5_frac_bankB_float1 | ffe_coeff_set5_frac_bankA_float3 | ffe_coeff_set5_frac_bankA_float2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set5_frac_bankB_float2 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set5_frac_bankB_float1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set5_frac_bankA_float3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set5_frac_bankA_float2 Reset: hex:0x00; |
+0x00000620 Register(32 bit) ffe_coeff_set5_frac_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e620 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set5_frac_bankC_float3 | ffe_coeff_set5_frac_bankC_float2 | ffe_coeff_set5_frac_bankC_float1 | ffe_coeff_set5_frac_bankB_float3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set5_frac_bankC_float3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set5_frac_bankC_float2 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set5_frac_bankC_float1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set5_frac_bankB_float3 Reset: hex:0x00; |
+0x00000624 Register(32 bit) ffe_coeff_set6_frac_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e624 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set6_frac_post1 | ffe_coeff_set6_frac_pre1 | ffe_coeff_set6_frac_pre2 | ffe_coeff_set6_frac_pre3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set6_frac_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set6_frac_pre1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set6_frac_pre2 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set6_frac_pre3 Reset: hex:0x00; |
+0x00000628 Register(32 bit) ffe_coeff_set6_frac_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e628 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set6_frac_post5 | ffe_coeff_set6_frac_post4 | ffe_coeff_set6_frac_post3 | ffe_coeff_set6_frac_post2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set6_frac_post5 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set6_frac_post4 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set6_frac_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set6_frac_post2 Reset: hex:0x00; |
+0x0000062c Register(32 bit) ffe_coeff_set6_frac_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e62c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set6_frac_post9 | ffe_coeff_set6_frac_post8 | ffe_coeff_set6_frac_post7 | ffe_coeff_set6_frac_post6 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set6_frac_post9 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set6_frac_post8 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set6_frac_post7 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set6_frac_post6 Reset: hex:0x00; |
+0x00000630 Register(32 bit) ffe_coeff_set6_frac_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e630 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set6_frac_bankA_float1 | ffe_coeff_set6_frac_post12 | ffe_coeff_set6_frac_post11 | ffe_coeff_set6_frac_post10 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set6_frac_bankA_float1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set6_frac_post12 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set6_frac_post11 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set6_frac_post10 Reset: hex:0x00; |
+0x00000634 Register(32 bit) ffe_coeff_set6_frac_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e634 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set6_frac_bankB_float2 | ffe_coeff_set6_frac_bankB_float1 | ffe_coeff_set6_frac_bankA_float3 | ffe_coeff_set6_frac_bankA_float2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set6_frac_bankB_float2 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set6_frac_bankB_float1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set6_frac_bankA_float3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set6_frac_bankA_float2 Reset: hex:0x00; |
+0x00000638 Register(32 bit) ffe_coeff_set6_frac_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e638 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set6_frac_bankC_float3 | ffe_coeff_set6_frac_bankC_float2 | ffe_coeff_set6_frac_bankC_float1 | ffe_coeff_set6_frac_bankB_float3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set6_frac_bankC_float3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set6_frac_bankC_float2 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set6_frac_bankC_float1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set6_frac_bankB_float3 Reset: hex:0x00; |
+0x0000063c Register(32 bit) ffe_coeff_set7_frac_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e63c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set7_frac_post1 | ffe_coeff_set7_frac_pre1 | ffe_coeff_set7_frac_pre2 | ffe_coeff_set7_frac_pre3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set7_frac_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set7_frac_pre1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set7_frac_pre2 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set7_frac_pre3 Reset: hex:0x00; |
+0x00000640 Register(32 bit) ffe_coeff_set7_frac_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e640 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set7_frac_post5 | ffe_coeff_set7_frac_post4 | ffe_coeff_set7_frac_post3 | ffe_coeff_set7_frac_post2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set7_frac_post5 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set7_frac_post4 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set7_frac_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set7_frac_post2 Reset: hex:0x00; |
+0x00000644 Register(32 bit) ffe_coeff_set7_frac_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e644 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set7_frac_post9 | ffe_coeff_set7_frac_post8 | ffe_coeff_set7_frac_post7 | ffe_coeff_set7_frac_post6 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set7_frac_post9 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set7_frac_post8 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set7_frac_post7 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set7_frac_post6 Reset: hex:0x00; |
+0x00000648 Register(32 bit) ffe_coeff_set7_frac_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e648 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set7_frac_bankA_float1 | ffe_coeff_set7_frac_post12 | ffe_coeff_set7_frac_post11 | ffe_coeff_set7_frac_post10 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set7_frac_bankA_float1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set7_frac_post12 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set7_frac_post11 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set7_frac_post10 Reset: hex:0x00; |
+0x0000064c Register(32 bit) ffe_coeff_set7_frac_4
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e64c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set7_frac_bankB_float2 | ffe_coeff_set7_frac_bankB_float1 | ffe_coeff_set7_frac_bankA_float3 | ffe_coeff_set7_frac_bankA_float2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set7_frac_bankB_float2 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set7_frac_bankB_float1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set7_frac_bankA_float3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set7_frac_bankA_float2 Reset: hex:0x00; |
+0x00000650 Register(32 bit) ffe_coeff_set7_frac_5
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e650 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set7_frac_bankC_float3 | ffe_coeff_set7_frac_bankC_float2 | ffe_coeff_set7_frac_bankC_float1 | ffe_coeff_set7_frac_bankB_float3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set7_frac_bankC_float3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set7_frac_bankC_float2 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set7_frac_bankC_float1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set7_frac_bankB_float3 Reset: hex:0x00; |
+0x00000654 Register(32 bit) ffe_coeff_set8_frac_0
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e654 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set8_frac_post1 | ffe_coeff_set8_frac_pre1 | ffe_coeff_set8_frac_pre2 | ffe_coeff_set8_frac_pre3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set8_frac_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set8_frac_pre1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set8_frac_pre2 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set8_frac_pre3 Reset: hex:0x00; |
+0x00000658 Register(32 bit) ffe_coeff_set8_frac_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e658 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set8_frac_post5 | ffe_coeff_set8_frac_post4 | ffe_coeff_set8_frac_post3 | ffe_coeff_set8_frac_post2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set8_frac_post5 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set8_frac_post4 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set8_frac_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set8_frac_post2 Reset: hex:0x00; |
+0x0000065c Register(32 bit) ffe_coeff_set8_frac_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e65c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set8_frac_post9 | ffe_coeff_set8_frac_post8 | ffe_coeff_set8_frac_post7 | ffe_coeff_set8_frac_post6 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set8_frac_post9 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set8_frac_post8 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set8_frac_post7 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set8_frac_post6 Reset: hex:0x00; |
+0x00000660 Register(32 bit) ffe_coeff_set8_frac_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e660 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set8_frac_bankA_float1 | ffe_coeff_set8_frac_post12 | ffe_coeff_set8_frac_post11 | ffe_coeff_set8_frac_post10 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set8_frac_bankA_float1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set8_frac_post12 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set8_frac_post11 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set8_frac_post10 Reset: hex:0x00; |
+0x00000664 Register(32 bit) ffe_coeff_set8_frac_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e664 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set8_frac_bankB_float2 | ffe_coeff_set8_frac_bankB_float1 | ffe_coeff_set8_frac_bankA_float3 | ffe_coeff_set8_frac_bankA_float2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set8_frac_bankB_float2 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set8_frac_bankB_float1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set8_frac_bankA_float3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set8_frac_bankA_float2 Reset: hex:0x00; |
+0x00000668 Register(32 bit) ffe_coeff_set8_frac_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e668 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set8_frac_bankC_float3 | ffe_coeff_set8_frac_bankC_float2 | ffe_coeff_set8_frac_bankC_float1 | ffe_coeff_set8_frac_bankB_float3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set8_frac_bankC_float3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set8_frac_bankC_float2 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set8_frac_bankC_float1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set8_frac_bankB_float3 Reset: hex:0x00; |
+0x0000066c Register(32 bit) ffe_coeff_set9_frac_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e66c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set9_frac_post1 | ffe_coeff_set9_frac_pre1 | ffe_coeff_set9_frac_pre2 | ffe_coeff_set9_frac_pre3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set9_frac_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set9_frac_pre1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set9_frac_pre2 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set9_frac_pre3 Reset: hex:0x00; |
+0x00000670 Register(32 bit) ffe_coeff_set9_frac_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e670 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set9_frac_post5 | ffe_coeff_set9_frac_post4 | ffe_coeff_set9_frac_post3 | ffe_coeff_set9_frac_post2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set9_frac_post5 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set9_frac_post4 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set9_frac_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set9_frac_post2 Reset: hex:0x00; |
+0x00000674 Register(32 bit) ffe_coeff_set9_frac_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e674 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set9_frac_post9 | ffe_coeff_set9_frac_post8 | ffe_coeff_set9_frac_post7 | ffe_coeff_set9_frac_post6 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set9_frac_post9 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set9_frac_post8 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set9_frac_post7 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set9_frac_post6 Reset: hex:0x00; |
+0x00000678 Register(32 bit) ffe_coeff_set9_frac_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e678 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set9_frac_bankA_float1 | ffe_coeff_set9_frac_post12 | ffe_coeff_set9_frac_post11 | ffe_coeff_set9_frac_post10 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set9_frac_bankA_float1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set9_frac_post12 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set9_frac_post11 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set9_frac_post10 Reset: hex:0x00; |
+0x0000067c Register(32 bit) ffe_coeff_set9_frac_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e67c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set9_frac_bankB_float2 | ffe_coeff_set9_frac_bankB_float1 | ffe_coeff_set9_frac_bankA_float3 | ffe_coeff_set9_frac_bankA_float2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set9_frac_bankB_float2 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set9_frac_bankB_float1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set9_frac_bankA_float3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set9_frac_bankA_float2 Reset: hex:0x00; |
+0x00000680 Register(32 bit) ffe_coeff_set9_frac_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e680 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set9_frac_bankC_float3 | ffe_coeff_set9_frac_bankC_float2 | ffe_coeff_set9_frac_bankC_float1 | ffe_coeff_set9_frac_bankB_float3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set9_frac_bankC_float3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set9_frac_bankC_float2 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set9_frac_bankC_float1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set9_frac_bankB_float3 Reset: hex:0x00; |
+0x00000684 Register(32 bit) ffe_coeff_set10_frac_0
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e684 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set10_frac_post1 | ffe_coeff_set10_frac_pre1 | ffe_coeff_set10_frac_pre2 | ffe_coeff_set10_frac_pre3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set10_frac_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set10_frac_pre1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set10_frac_pre2 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set10_frac_pre3 Reset: hex:0x00; |
+0x00000688 Register(32 bit) ffe_coeff_set10_frac_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e688 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set10_frac_post5 | ffe_coeff_set10_frac_post4 | ffe_coeff_set10_frac_post3 | ffe_coeff_set10_frac_post2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set10_frac_post5 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set10_frac_post4 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set10_frac_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set10_frac_post2 Reset: hex:0x00; |
+0x0000068c Register(32 bit) ffe_coeff_set10_frac_2
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e68c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set10_frac_post9 | ffe_coeff_set10_frac_post8 | ffe_coeff_set10_frac_post7 | ffe_coeff_set10_frac_post6 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set10_frac_post9 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set10_frac_post8 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set10_frac_post7 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set10_frac_post6 Reset: hex:0x00; |
+0x00000690 Register(32 bit) ffe_coeff_set10_frac_3
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e690 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set10_frac_bankA_float1 | ffe_coeff_set10_frac_post12 | ffe_coeff_set10_frac_post11 | ffe_coeff_set10_frac_post10 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set10_frac_bankA_float1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set10_frac_post12 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set10_frac_post11 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set10_frac_post10 Reset: hex:0x00; |
+0x00000694 Register(32 bit) ffe_coeff_set10_frac_4
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e694 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set10_frac_bankB_float2 | ffe_coeff_set10_frac_bankB_float1 | ffe_coeff_set10_frac_bankA_float3 | ffe_coeff_set10_frac_bankA_float2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set10_frac_bankB_float2 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set10_frac_bankB_float1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set10_frac_bankA_float3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set10_frac_bankA_float2 Reset: hex:0x00; |
+0x00000698 Register(32 bit) ffe_coeff_set10_frac_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e698 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set10_frac_bankC_float3 | ffe_coeff_set10_frac_bankC_float2 | ffe_coeff_set10_frac_bankC_float1 | ffe_coeff_set10_frac_bankB_float3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set10_frac_bankC_float3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set10_frac_bankC_float2 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set10_frac_bankC_float1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set10_frac_bankB_float3 Reset: hex:0x00; |
+0x0000069c Register(32 bit) ffe_coeff_set11_frac_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e69c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set11_frac_post1 | ffe_coeff_set11_frac_pre1 | ffe_coeff_set11_frac_pre2 | ffe_coeff_set11_frac_pre3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set11_frac_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set11_frac_pre1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set11_frac_pre2 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set11_frac_pre3 Reset: hex:0x00; |
+0x000006a0 Register(32 bit) ffe_coeff_set11_frac_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6a0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set11_frac_post5 | ffe_coeff_set11_frac_post4 | ffe_coeff_set11_frac_post3 | ffe_coeff_set11_frac_post2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set11_frac_post5 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set11_frac_post4 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set11_frac_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set11_frac_post2 Reset: hex:0x00; |
+0x000006a4 Register(32 bit) ffe_coeff_set11_frac_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6a4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set11_frac_post9 | ffe_coeff_set11_frac_post8 | ffe_coeff_set11_frac_post7 | ffe_coeff_set11_frac_post6 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set11_frac_post9 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set11_frac_post8 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set11_frac_post7 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set11_frac_post6 Reset: hex:0x00; |
+0x000006a8 Register(32 bit) ffe_coeff_set11_frac_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6a8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set11_frac_bankA_float1 | ffe_coeff_set11_frac_post12 | ffe_coeff_set11_frac_post11 | ffe_coeff_set11_frac_post10 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set11_frac_bankA_float1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set11_frac_post12 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set11_frac_post11 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set11_frac_post10 Reset: hex:0x00; |
+0x000006ac Register(32 bit) ffe_coeff_set11_frac_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6ac at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set11_frac_bankB_float2 | ffe_coeff_set11_frac_bankB_float1 | ffe_coeff_set11_frac_bankA_float3 | ffe_coeff_set11_frac_bankA_float2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set11_frac_bankB_float2 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set11_frac_bankB_float1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set11_frac_bankA_float3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set11_frac_bankA_float2 Reset: hex:0x00; |
+0x000006b0 Register(32 bit) ffe_coeff_set11_frac_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6b0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set11_frac_bankC_float3 | ffe_coeff_set11_frac_bankC_float2 | ffe_coeff_set11_frac_bankC_float1 | ffe_coeff_set11_frac_bankB_float3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set11_frac_bankC_float3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set11_frac_bankC_float2 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set11_frac_bankC_float1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set11_frac_bankB_float3 Reset: hex:0x00; |
+0x000006b4 Register(32 bit) ffe_coeff_set12_frac_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6b4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set12_frac_post1 | ffe_coeff_set12_frac_pre1 | ffe_coeff_set12_frac_pre2 | ffe_coeff_set12_frac_pre3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set12_frac_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set12_frac_pre1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set12_frac_pre2 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set12_frac_pre3 Reset: hex:0x00; |
+0x000006b8 Register(32 bit) ffe_coeff_set12_frac_1
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6b8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set12_frac_post5 | ffe_coeff_set12_frac_post4 | ffe_coeff_set12_frac_post3 | ffe_coeff_set12_frac_post2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set12_frac_post5 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set12_frac_post4 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set12_frac_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set12_frac_post2 Reset: hex:0x00; |
+0x000006bc Register(32 bit) ffe_coeff_set12_frac_2
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6bc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set12_frac_post9 | ffe_coeff_set12_frac_post8 | ffe_coeff_set12_frac_post7 | ffe_coeff_set12_frac_post6 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set12_frac_post9 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set12_frac_post8 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set12_frac_post7 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set12_frac_post6 Reset: hex:0x00; |
+0x000006c0 Register(32 bit) ffe_coeff_set12_frac_3
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6c0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set12_frac_bankA_float1 | ffe_coeff_set12_frac_post12 | ffe_coeff_set12_frac_post11 | ffe_coeff_set12_frac_post10 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set12_frac_bankA_float1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set12_frac_post12 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set12_frac_post11 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set12_frac_post10 Reset: hex:0x00; |
+0x000006c4 Register(32 bit) ffe_coeff_set12_frac_4
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6c4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set12_frac_bankB_float2 | ffe_coeff_set12_frac_bankB_float1 | ffe_coeff_set12_frac_bankA_float3 | ffe_coeff_set12_frac_bankA_float2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set12_frac_bankB_float2 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set12_frac_bankB_float1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set12_frac_bankA_float3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set12_frac_bankA_float2 Reset: hex:0x00; |
+0x000006c8 Register(32 bit) ffe_coeff_set12_frac_5
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6c8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set12_frac_bankC_float3 | ffe_coeff_set12_frac_bankC_float2 | ffe_coeff_set12_frac_bankC_float1 | ffe_coeff_set12_frac_bankB_float3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set12_frac_bankC_float3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set12_frac_bankC_float2 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set12_frac_bankC_float1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set12_frac_bankB_float3 Reset: hex:0x00; |
+0x000006cc Register(32 bit) ffe_coeff_set13_frac_0
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6cc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set13_frac_post1 | ffe_coeff_set13_frac_pre1 | ffe_coeff_set13_frac_pre2 | ffe_coeff_set13_frac_pre3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set13_frac_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set13_frac_pre1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set13_frac_pre2 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set13_frac_pre3 Reset: hex:0x00; |
+0x000006d0 Register(32 bit) ffe_coeff_set13_frac_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6d0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set13_frac_post5 | ffe_coeff_set13_frac_post4 | ffe_coeff_set13_frac_post3 | ffe_coeff_set13_frac_post2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set13_frac_post5 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set13_frac_post4 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set13_frac_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set13_frac_post2 Reset: hex:0x00; |
+0x000006d4 Register(32 bit) ffe_coeff_set13_frac_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6d4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set13_frac_post9 | ffe_coeff_set13_frac_post8 | ffe_coeff_set13_frac_post7 | ffe_coeff_set13_frac_post6 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set13_frac_post9 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set13_frac_post8 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set13_frac_post7 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set13_frac_post6 Reset: hex:0x00; |
+0x000006d8 Register(32 bit) ffe_coeff_set13_frac_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6d8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set13_frac_bankA_float1 | ffe_coeff_set13_frac_post12 | ffe_coeff_set13_frac_post11 | ffe_coeff_set13_frac_post10 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set13_frac_bankA_float1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set13_frac_post12 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set13_frac_post11 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set13_frac_post10 Reset: hex:0x00; |
+0x000006dc Register(32 bit) ffe_coeff_set13_frac_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6dc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set13_frac_bankB_float2 | ffe_coeff_set13_frac_bankB_float1 | ffe_coeff_set13_frac_bankA_float3 | ffe_coeff_set13_frac_bankA_float2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set13_frac_bankB_float2 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set13_frac_bankB_float1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set13_frac_bankA_float3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set13_frac_bankA_float2 Reset: hex:0x00; |
+0x000006e0 Register(32 bit) ffe_coeff_set13_frac_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6e0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set13_frac_bankC_float3 | ffe_coeff_set13_frac_bankC_float2 | ffe_coeff_set13_frac_bankC_float1 | ffe_coeff_set13_frac_bankB_float3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set13_frac_bankC_float3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set13_frac_bankC_float2 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set13_frac_bankC_float1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set13_frac_bankB_float3 Reset: hex:0x00; |
+0x000006e4 Register(32 bit) ffe_coeff_set14_frac_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6e4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set14_frac_post1 | ffe_coeff_set14_frac_pre1 | ffe_coeff_set14_frac_pre2 | ffe_coeff_set14_frac_pre3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set14_frac_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set14_frac_pre1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set14_frac_pre2 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set14_frac_pre3 Reset: hex:0x00; |
+0x000006e8 Register(32 bit) ffe_coeff_set14_frac_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6e8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set14_frac_post5 | ffe_coeff_set14_frac_post4 | ffe_coeff_set14_frac_post3 | ffe_coeff_set14_frac_post2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set14_frac_post5 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set14_frac_post4 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set14_frac_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set14_frac_post2 Reset: hex:0x00; |
+0x000006ec Register(32 bit) ffe_coeff_set14_frac_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6ec at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set14_frac_post9 | ffe_coeff_set14_frac_post8 | ffe_coeff_set14_frac_post7 | ffe_coeff_set14_frac_post6 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set14_frac_post9 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set14_frac_post8 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set14_frac_post7 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set14_frac_post6 Reset: hex:0x00; |
+0x000006f0 Register(32 bit) ffe_coeff_set14_frac_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6f0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set14_frac_bankA_float1 | ffe_coeff_set14_frac_post12 | ffe_coeff_set14_frac_post11 | ffe_coeff_set14_frac_post10 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set14_frac_bankA_float1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set14_frac_post12 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set14_frac_post11 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set14_frac_post10 Reset: hex:0x00; |
+0x000006f4 Register(32 bit) ffe_coeff_set14_frac_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6f4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set14_frac_bankB_float2 | ffe_coeff_set14_frac_bankB_float1 | ffe_coeff_set14_frac_bankA_float3 | ffe_coeff_set14_frac_bankA_float2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set14_frac_bankB_float2 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set14_frac_bankB_float1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set14_frac_bankA_float3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set14_frac_bankA_float2 Reset: hex:0x00; |
+0x000006f8 Register(32 bit) ffe_coeff_set14_frac_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6f8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set14_frac_bankC_float3 | ffe_coeff_set14_frac_bankC_float2 | ffe_coeff_set14_frac_bankC_float1 | ffe_coeff_set14_frac_bankB_float3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set14_frac_bankC_float3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set14_frac_bankC_float2 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set14_frac_bankC_float1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set14_frac_bankB_float3 Reset: hex:0x00; |
+0x000006fc Register(32 bit) ffe_coeff_set15_frac_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e6fc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set15_frac_post1 | ffe_coeff_set15_frac_pre1 | ffe_coeff_set15_frac_pre2 | ffe_coeff_set15_frac_pre3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set15_frac_post1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set15_frac_pre1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set15_frac_pre2 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set15_frac_pre3 Reset: hex:0x00; |
+0x00000700 Register(32 bit) ffe_coeff_set15_frac_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e700 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set15_frac_post5 | ffe_coeff_set15_frac_post4 | ffe_coeff_set15_frac_post3 | ffe_coeff_set15_frac_post2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set15_frac_post5 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set15_frac_post4 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set15_frac_post3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set15_frac_post2 Reset: hex:0x00; |
+0x00000704 Register(32 bit) ffe_coeff_set15_frac_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e704 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set15_frac_post9 | ffe_coeff_set15_frac_post8 | ffe_coeff_set15_frac_post7 | ffe_coeff_set15_frac_post6 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set15_frac_post9 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set15_frac_post8 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set15_frac_post7 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set15_frac_post6 Reset: hex:0x00; |
+0x00000708 Register(32 bit) ffe_coeff_set15_frac_3
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e708 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set15_frac_bankA_float1 | ffe_coeff_set15_frac_post12 | ffe_coeff_set15_frac_post11 | ffe_coeff_set15_frac_post10 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set15_frac_bankA_float1 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set15_frac_post12 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set15_frac_post11 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set15_frac_post10 Reset: hex:0x00; |
+0x0000070c Register(32 bit) ffe_coeff_set15_frac_4
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e70c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set15_frac_bankB_float2 | ffe_coeff_set15_frac_bankB_float1 | ffe_coeff_set15_frac_bankA_float3 | ffe_coeff_set15_frac_bankA_float2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set15_frac_bankB_float2 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set15_frac_bankB_float1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set15_frac_bankA_float3 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set15_frac_bankA_float2 Reset: hex:0x00; |
+0x00000710 Register(32 bit) ffe_coeff_set15_frac_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e710 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_coeff_set15_frac_bankC_float3 | ffe_coeff_set15_frac_bankC_float2 | ffe_coeff_set15_frac_bankC_float1 | ffe_coeff_set15_frac_bankB_float3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_coeff_set15_frac_bankC_float3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_coeff_set15_frac_bankC_float2 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_coeff_set15_frac_bankC_float1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_coeff_set15_frac_bankB_float3 Reset: hex:0x00; |
+0x00000714 Register(32 bit) ffe_err_level_frac_set0_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e714 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_err_level_frac_set0_p3 | ffe_err_level_frac_set0_p1 | ffe_err_level_frac_set0_m1 | ffe_err_level_frac_set0_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_err_level_frac_set0_p3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_err_level_frac_set0_p1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_err_level_frac_set0_m1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_err_level_frac_set0_m3 Reset: hex:0x00; |
+0x00000718 Register(32 bit) ffe_err_level_frac_set1_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e718 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_err_level_frac_set1_p3 | ffe_err_level_frac_set1_p1 | ffe_err_level_frac_set1_m1 | ffe_err_level_frac_set1_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_err_level_frac_set1_p3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_err_level_frac_set1_p1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_err_level_frac_set1_m1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_err_level_frac_set1_m3 Reset: hex:0x00; |
+0x0000071c Register(32 bit) ffe_err_level_frac_set2_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e71c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_err_level_frac_set2_p3 | ffe_err_level_frac_set2_p1 | ffe_err_level_frac_set2_m1 | ffe_err_level_frac_set2_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_err_level_frac_set2_p3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_err_level_frac_set2_p1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_err_level_frac_set2_m1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_err_level_frac_set2_m3 Reset: hex:0x00; |
+0x00000720 Register(32 bit) ffe_err_level_frac_set3_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e720 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_err_level_frac_set3_p3 | ffe_err_level_frac_set3_p1 | ffe_err_level_frac_set3_m1 | ffe_err_level_frac_set3_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_err_level_frac_set3_p3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_err_level_frac_set3_p1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_err_level_frac_set3_m1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_err_level_frac_set3_m3 Reset: hex:0x00; |
+0x00000724 Register(32 bit) ffe_err_level_frac_set4_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e724 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_err_level_frac_set4_p3 | ffe_err_level_frac_set4_p1 | ffe_err_level_frac_set4_m1 | ffe_err_level_frac_set4_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_err_level_frac_set4_p3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_err_level_frac_set4_p1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_err_level_frac_set4_m1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_err_level_frac_set4_m3 Reset: hex:0x00; |
+0x00000728 Register(32 bit) ffe_err_level_frac_set5_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e728 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_err_level_frac_set5_p3 | ffe_err_level_frac_set5_p1 | ffe_err_level_frac_set5_m1 | ffe_err_level_frac_set5_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_err_level_frac_set5_p3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_err_level_frac_set5_p1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_err_level_frac_set5_m1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_err_level_frac_set5_m3 Reset: hex:0x00; |
+0x0000072c Register(32 bit) ffe_err_level_frac_set6_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e72c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_err_level_frac_set6_p3 | ffe_err_level_frac_set6_p1 | ffe_err_level_frac_set6_m1 | ffe_err_level_frac_set6_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_err_level_frac_set6_p3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_err_level_frac_set6_p1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_err_level_frac_set6_m1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_err_level_frac_set6_m3 Reset: hex:0x00; |
+0x00000730 Register(32 bit) ffe_err_level_frac_set7_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e730 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_err_level_frac_set7_p3 | ffe_err_level_frac_set7_p1 | ffe_err_level_frac_set7_m1 | ffe_err_level_frac_set7_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_err_level_frac_set7_p3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_err_level_frac_set7_p1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_err_level_frac_set7_m1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_err_level_frac_set7_m3 Reset: hex:0x00; |
+0x00000734 Register(32 bit) ffe_err_level_frac_set8_0
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e734 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_err_level_frac_set8_p3 | ffe_err_level_frac_set8_p1 | ffe_err_level_frac_set8_m1 | ffe_err_level_frac_set8_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_err_level_frac_set8_p3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_err_level_frac_set8_p1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_err_level_frac_set8_m1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_err_level_frac_set8_m3 Reset: hex:0x00; |
+0x00000738 Register(32 bit) ffe_err_level_frac_set9_0
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e738 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_err_level_frac_set9_p3 | ffe_err_level_frac_set9_p1 | ffe_err_level_frac_set9_m1 | ffe_err_level_frac_set9_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_err_level_frac_set9_p3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_err_level_frac_set9_p1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_err_level_frac_set9_m1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_err_level_frac_set9_m3 Reset: hex:0x00; |
+0x0000073c Register(32 bit) ffe_err_level_frac_set10_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e73c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_err_level_frac_set10_p3 | ffe_err_level_frac_set10_p1 | ffe_err_level_frac_set10_m1 | ffe_err_level_frac_set10_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_err_level_frac_set10_p3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_err_level_frac_set10_p1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_err_level_frac_set10_m1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_err_level_frac_set10_m3 Reset: hex:0x00; |
+0x00000740 Register(32 bit) ffe_err_level_frac_set11_0
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e740 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_err_level_frac_set11_p3 | ffe_err_level_frac_set11_p1 | ffe_err_level_frac_set11_m1 | ffe_err_level_frac_set11_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_err_level_frac_set11_p3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_err_level_frac_set11_p1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_err_level_frac_set11_m1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_err_level_frac_set11_m3 Reset: hex:0x00; |
+0x00000744 Register(32 bit) ffe_err_level_frac_set12_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e744 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_err_level_frac_set12_p3 | ffe_err_level_frac_set12_p1 | ffe_err_level_frac_set12_m1 | ffe_err_level_frac_set12_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_err_level_frac_set12_p3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_err_level_frac_set12_p1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_err_level_frac_set12_m1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_err_level_frac_set12_m3 Reset: hex:0x00; |
+0x00000748 Register(32 bit) ffe_err_level_frac_set13_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e748 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_err_level_frac_set13_p3 | ffe_err_level_frac_set13_p1 | ffe_err_level_frac_set13_m1 | ffe_err_level_frac_set13_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_err_level_frac_set13_p3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_err_level_frac_set13_p1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_err_level_frac_set13_m1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_err_level_frac_set13_m3 Reset: hex:0x00; |
+0x0000074c Register(32 bit) ffe_err_level_frac_set14_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e74c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_err_level_frac_set14_p3 | ffe_err_level_frac_set14_p1 | ffe_err_level_frac_set14_m1 | ffe_err_level_frac_set14_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_err_level_frac_set14_p3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_err_level_frac_set14_p1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_err_level_frac_set14_m1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_err_level_frac_set14_m3 Reset: hex:0x00; |
+0x00000750 Register(32 bit) ffe_err_level_frac_set15_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e750 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_err_level_frac_set15_p3 | ffe_err_level_frac_set15_p1 | ffe_err_level_frac_set15_m1 | ffe_err_level_frac_set15_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ffe_err_level_frac_set15_p3 Reset: hex:0x00; |
| [23:16] RW/V |
ffe_err_level_frac_set15_p1 Reset: hex:0x00; |
| [15:08] RW/V |
ffe_err_level_frac_set15_m1 Reset: hex:0x00; |
| [07:00] RW/V |
ffe_err_level_frac_set15_m3 Reset: hex:0x00; |
+0x00000754 Register(32 bit) adc_err_level_frac_set0_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e754 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | adc_err_level_frac_set0_p3 | adc_err_level_frac_set0_p1 | adc_err_level_frac_set0_m1 | adc_err_level_frac_set0_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
adc_err_level_frac_set0_p3 Reset: hex:0x00; |
| [23:16] RW/V |
adc_err_level_frac_set0_p1 Reset: hex:0x00; |
| [15:08] RW/V |
adc_err_level_frac_set0_m1 Reset: hex:0x00; |
| [07:00] RW/V |
adc_err_level_frac_set0_m3 Reset: hex:0x00; |
+0x00000758 Register(32 bit) adc_err_level_frac_set1_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e758 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | adc_err_level_frac_set1_p3 | adc_err_level_frac_set1_p1 | adc_err_level_frac_set1_m1 | adc_err_level_frac_set1_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
adc_err_level_frac_set1_p3 Reset: hex:0x00; |
| [23:16] RW/V |
adc_err_level_frac_set1_p1 Reset: hex:0x00; |
| [15:08] RW/V |
adc_err_level_frac_set1_m1 Reset: hex:0x00; |
| [07:00] RW/V |
adc_err_level_frac_set1_m3 Reset: hex:0x00; |
+0x0000075c Register(32 bit) adc_err_level_frac_set2_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e75c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | adc_err_level_frac_set2_p3 | adc_err_level_frac_set2_p1 | adc_err_level_frac_set2_m1 | adc_err_level_frac_set2_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
adc_err_level_frac_set2_p3 Reset: hex:0x00; |
| [23:16] RW/V |
adc_err_level_frac_set2_p1 Reset: hex:0x00; |
| [15:08] RW/V |
adc_err_level_frac_set2_m1 Reset: hex:0x00; |
| [07:00] RW/V |
adc_err_level_frac_set2_m3 Reset: hex:0x00; |
+0x00000760 Register(32 bit) adc_err_level_frac_set3_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e760 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | adc_err_level_frac_set3_p3 | adc_err_level_frac_set3_p1 | adc_err_level_frac_set3_m1 | adc_err_level_frac_set3_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
adc_err_level_frac_set3_p3 Reset: hex:0x00; |
| [23:16] RW/V |
adc_err_level_frac_set3_p1 Reset: hex:0x00; |
| [15:08] RW/V |
adc_err_level_frac_set3_m1 Reset: hex:0x00; |
| [07:00] RW/V |
adc_err_level_frac_set3_m3 Reset: hex:0x00; |
+0x00000764 Register(32 bit) adc_err_level_frac_set4_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e764 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | adc_err_level_frac_set4_p3 | adc_err_level_frac_set4_p1 | adc_err_level_frac_set4_m1 | adc_err_level_frac_set4_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
adc_err_level_frac_set4_p3 Reset: hex:0x00; |
| [23:16] RW/V |
adc_err_level_frac_set4_p1 Reset: hex:0x00; |
| [15:08] RW/V |
adc_err_level_frac_set4_m1 Reset: hex:0x00; |
| [07:00] RW/V |
adc_err_level_frac_set4_m3 Reset: hex:0x00; |
+0x00000768 Register(32 bit) adc_err_level_frac_set5_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e768 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | adc_err_level_frac_set5_p3 | adc_err_level_frac_set5_p1 | adc_err_level_frac_set5_m1 | adc_err_level_frac_set5_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
adc_err_level_frac_set5_p3 Reset: hex:0x00; |
| [23:16] RW/V |
adc_err_level_frac_set5_p1 Reset: hex:0x00; |
| [15:08] RW/V |
adc_err_level_frac_set5_m1 Reset: hex:0x00; |
| [07:00] RW/V |
adc_err_level_frac_set5_m3 Reset: hex:0x00; |
+0x0000076c Register(32 bit) adc_err_level_frac_set6_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e76c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | adc_err_level_frac_set6_p3 | adc_err_level_frac_set6_p1 | adc_err_level_frac_set6_m1 | adc_err_level_frac_set6_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
adc_err_level_frac_set6_p3 Reset: hex:0x00; |
| [23:16] RW/V |
adc_err_level_frac_set6_p1 Reset: hex:0x00; |
| [15:08] RW/V |
adc_err_level_frac_set6_m1 Reset: hex:0x00; |
| [07:00] RW/V |
adc_err_level_frac_set6_m3 Reset: hex:0x00; |
+0x00000770 Register(32 bit) adc_err_level_frac_set7_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e770 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | adc_err_level_frac_set7_p3 | adc_err_level_frac_set7_p1 | adc_err_level_frac_set7_m1 | adc_err_level_frac_set7_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
adc_err_level_frac_set7_p3 Reset: hex:0x00; |
| [23:16] RW/V |
adc_err_level_frac_set7_p1 Reset: hex:0x00; |
| [15:08] RW/V |
adc_err_level_frac_set7_m1 Reset: hex:0x00; |
| [07:00] RW/V |
adc_err_level_frac_set7_m3 Reset: hex:0x00; |
+0x00000774 Register(32 bit) adc_err_level_frac_set8_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e774 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | adc_err_level_frac_set8_p3 | adc_err_level_frac_set8_p1 | adc_err_level_frac_set8_m1 | adc_err_level_frac_set8_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
adc_err_level_frac_set8_p3 Reset: hex:0x00; |
| [23:16] RW/V |
adc_err_level_frac_set8_p1 Reset: hex:0x00; |
| [15:08] RW/V |
adc_err_level_frac_set8_m1 Reset: hex:0x00; |
| [07:00] RW/V |
adc_err_level_frac_set8_m3 Reset: hex:0x00; |
+0x00000778 Register(32 bit) adc_err_level_frac_set9_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e778 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | adc_err_level_frac_set9_p3 | adc_err_level_frac_set9_p1 | adc_err_level_frac_set9_m1 | adc_err_level_frac_set9_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
adc_err_level_frac_set9_p3 Reset: hex:0x00; |
| [23:16] RW/V |
adc_err_level_frac_set9_p1 Reset: hex:0x00; |
| [15:08] RW/V |
adc_err_level_frac_set9_m1 Reset: hex:0x00; |
| [07:00] RW/V |
adc_err_level_frac_set9_m3 Reset: hex:0x00; |
+0x0000077c Register(32 bit) adc_err_level_frac_set10_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e77c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | adc_err_level_frac_set10_p3 | adc_err_level_frac_set10_p1 | adc_err_level_frac_set10_m1 | adc_err_level_frac_set10_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
adc_err_level_frac_set10_p3 Reset: hex:0x00; |
| [23:16] RW/V |
adc_err_level_frac_set10_p1 Reset: hex:0x00; |
| [15:08] RW/V |
adc_err_level_frac_set10_m1 Reset: hex:0x00; |
| [07:00] RW/V |
adc_err_level_frac_set10_m3 Reset: hex:0x00; |
+0x00000780 Register(32 bit) adc_err_level_frac_set11_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e780 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | adc_err_level_frac_set11_p3 | adc_err_level_frac_set11_p1 | adc_err_level_frac_set11_m1 | adc_err_level_frac_set11_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
adc_err_level_frac_set11_p3 Reset: hex:0x00; |
| [23:16] RW/V |
adc_err_level_frac_set11_p1 Reset: hex:0x00; |
| [15:08] RW/V |
adc_err_level_frac_set11_m1 Reset: hex:0x00; |
| [07:00] RW/V |
adc_err_level_frac_set11_m3 Reset: hex:0x00; |
+0x00000784 Register(32 bit) adc_err_level_frac_set12_0
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e784 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | adc_err_level_frac_set12_p3 | adc_err_level_frac_set12_p1 | adc_err_level_frac_set12_m1 | adc_err_level_frac_set12_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
adc_err_level_frac_set12_p3 Reset: hex:0x00; |
| [23:16] RW/V |
adc_err_level_frac_set12_p1 Reset: hex:0x00; |
| [15:08] RW/V |
adc_err_level_frac_set12_m1 Reset: hex:0x00; |
| [07:00] RW/V |
adc_err_level_frac_set12_m3 Reset: hex:0x00; |
+0x00000788 Register(32 bit) adc_err_level_frac_set13_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e788 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | adc_err_level_frac_set13_p3 | adc_err_level_frac_set13_p1 | adc_err_level_frac_set13_m1 | adc_err_level_frac_set13_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
adc_err_level_frac_set13_p3 Reset: hex:0x00; |
| [23:16] RW/V |
adc_err_level_frac_set13_p1 Reset: hex:0x00; |
| [15:08] RW/V |
adc_err_level_frac_set13_m1 Reset: hex:0x00; |
| [07:00] RW/V |
adc_err_level_frac_set13_m3 Reset: hex:0x00; |
+0x0000078c Register(32 bit) adc_err_level_frac_set14_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e78c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | adc_err_level_frac_set14_p3 | adc_err_level_frac_set14_p1 | adc_err_level_frac_set14_m1 | adc_err_level_frac_set14_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
adc_err_level_frac_set14_p3 Reset: hex:0x00; |
| [23:16] RW/V |
adc_err_level_frac_set14_p1 Reset: hex:0x00; |
| [15:08] RW/V |
adc_err_level_frac_set14_m1 Reset: hex:0x00; |
| [07:00] RW/V |
adc_err_level_frac_set14_m3 Reset: hex:0x00; |
+0x00000790 Register(32 bit) adc_err_level_frac_set15_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e790 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | adc_err_level_frac_set15_p3 | adc_err_level_frac_set15_p1 | adc_err_level_frac_set15_m1 | adc_err_level_frac_set15_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
adc_err_level_frac_set15_p3 Reset: hex:0x00; |
| [23:16] RW/V |
adc_err_level_frac_set15_p1 Reset: hex:0x00; |
| [15:08] RW/V |
adc_err_level_frac_set15_m1 Reset: hex:0x00; |
| [07:00] RW/V |
adc_err_level_frac_set15_m3 Reset: hex:0x00; |
+0x00000794 Register(32 bit) affe_lms_set0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e794 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x80808080 | ||
| Undefined | 0x80808080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_coeff_set0_post2 | - | affe_coeff_set0_post1 | - | affe_coeff_set0_pre1 | - | affe_coeff_set0_pre2 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [30:24] RW/V |
affe_coeff_set0_post2 Reset: hex:0x00; |
| [22:16] RW/V |
affe_coeff_set0_post1 Reset: hex:0x00; |
| [14:08] RW/V |
affe_coeff_set0_pre1 Reset: hex:0x00; |
| [06:00] RW/V |
affe_coeff_set0_pre2 Reset: hex:0x00; |
+0x00000798 Register(32 bit) affe_lms_set1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e798 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x80808080 | ||
| Undefined | 0x80808080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_coeff_set1_post2 | - | affe_coeff_set1_post1 | - | affe_coeff_set1_pre1 | - | affe_coeff_set1_pre2 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [30:24] RW/V |
affe_coeff_set1_post2 Reset: hex:0x00; |
| [22:16] RW/V |
affe_coeff_set1_post1 Reset: hex:0x00; |
| [14:08] RW/V |
affe_coeff_set1_pre1 Reset: hex:0x00; |
| [06:00] RW/V |
affe_coeff_set1_pre2 Reset: hex:0x00; |
+0x0000079c Register(32 bit) affe_lms_set2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e79c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x80808080 | ||
| Undefined | 0x80808080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_coeff_set2_post2 | - | affe_coeff_set2_post1 | - | affe_coeff_set2_pre1 | - | affe_coeff_set2_pre2 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [30:24] RW/V |
affe_coeff_set2_post2 Reset: hex:0x00; |
| [22:16] RW/V |
affe_coeff_set2_post1 Reset: hex:0x00; |
| [14:08] RW/V |
affe_coeff_set2_pre1 Reset: hex:0x00; |
| [06:00] RW/V |
affe_coeff_set2_pre2 Reset: hex:0x00; |
+0x000007a0 Register(32 bit) affe_lms_set3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7a0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x80808080 | ||
| Undefined | 0x80808080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_coeff_set3_post2 | - | affe_coeff_set3_post1 | - | affe_coeff_set3_pre1 | - | affe_coeff_set3_pre2 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [30:24] RW/V |
affe_coeff_set3_post2 Reset: hex:0x00; |
| [22:16] RW/V |
affe_coeff_set3_post1 Reset: hex:0x00; |
| [14:08] RW/V |
affe_coeff_set3_pre1 Reset: hex:0x00; |
| [06:00] RW/V |
affe_coeff_set3_pre2 Reset: hex:0x00; |
+0x000007a4 Register(32 bit) affe_lms_set4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7a4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x80808080 | ||
| Undefined | 0x80808080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_coeff_set4_post2 | - | affe_coeff_set4_post1 | - | affe_coeff_set4_pre1 | - | affe_coeff_set4_pre2 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [30:24] RW/V |
affe_coeff_set4_post2 Reset: hex:0x00; |
| [22:16] RW/V |
affe_coeff_set4_post1 Reset: hex:0x00; |
| [14:08] RW/V |
affe_coeff_set4_pre1 Reset: hex:0x00; |
| [06:00] RW/V |
affe_coeff_set4_pre2 Reset: hex:0x00; |
+0x000007a8 Register(32 bit) affe_lms_set5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7a8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x80808080 | ||
| Undefined | 0x80808080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_coeff_set5_post2 | - | affe_coeff_set5_post1 | - | affe_coeff_set5_pre1 | - | affe_coeff_set5_pre2 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [30:24] RW/V |
affe_coeff_set5_post2 Reset: hex:0x00; |
| [22:16] RW/V |
affe_coeff_set5_post1 Reset: hex:0x00; |
| [14:08] RW/V |
affe_coeff_set5_pre1 Reset: hex:0x00; |
| [06:00] RW/V |
affe_coeff_set5_pre2 Reset: hex:0x00; |
+0x000007ac Register(32 bit) affe_lms_set6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7ac at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x80808080 | ||
| Undefined | 0x80808080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_coeff_set6_post2 | - | affe_coeff_set6_post1 | - | affe_coeff_set6_pre1 | - | affe_coeff_set6_pre2 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [30:24] RW/V |
affe_coeff_set6_post2 Reset: hex:0x00; |
| [22:16] RW/V |
affe_coeff_set6_post1 Reset: hex:0x00; |
| [14:08] RW/V |
affe_coeff_set6_pre1 Reset: hex:0x00; |
| [06:00] RW/V |
affe_coeff_set6_pre2 Reset: hex:0x00; |
+0x000007b0 Register(32 bit) affe_lms_set7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7b0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x80808080 | ||
| Undefined | 0x80808080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_coeff_set7_post2 | - | affe_coeff_set7_post1 | - | affe_coeff_set7_pre1 | - | affe_coeff_set7_pre2 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [30:24] RW/V |
affe_coeff_set7_post2 Reset: hex:0x00; |
| [22:16] RW/V |
affe_coeff_set7_post1 Reset: hex:0x00; |
| [14:08] RW/V |
affe_coeff_set7_pre1 Reset: hex:0x00; |
| [06:00] RW/V |
affe_coeff_set7_pre2 Reset: hex:0x00; |
+0x000007b4 Register(32 bit) affe_lms_set8
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7b4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x80808080 | ||
| Undefined | 0x80808080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_coeff_set8_post2 | - | affe_coeff_set8_post1 | - | affe_coeff_set8_pre1 | - | affe_coeff_set8_pre2 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [30:24] RW/V |
affe_coeff_set8_post2 Reset: hex:0x00; |
| [22:16] RW/V |
affe_coeff_set8_post1 Reset: hex:0x00; |
| [14:08] RW/V |
affe_coeff_set8_pre1 Reset: hex:0x00; |
| [06:00] RW/V |
affe_coeff_set8_pre2 Reset: hex:0x00; |
+0x000007b8 Register(32 bit) affe_lms_set9
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7b8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x80808080 | ||
| Undefined | 0x80808080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_coeff_set9_post2 | - | affe_coeff_set9_post1 | - | affe_coeff_set9_pre1 | - | affe_coeff_set9_pre2 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [30:24] RW/V |
affe_coeff_set9_post2 Reset: hex:0x00; |
| [22:16] RW/V |
affe_coeff_set9_post1 Reset: hex:0x00; |
| [14:08] RW/V |
affe_coeff_set9_pre1 Reset: hex:0x00; |
| [06:00] RW/V |
affe_coeff_set9_pre2 Reset: hex:0x00; |
+0x000007bc Register(32 bit) affe_lms_set10
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7bc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x80808080 | ||
| Undefined | 0x80808080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_coeff_set10_post2 | - | affe_coeff_set10_post1 | - | affe_coeff_set10_pre1 | - | affe_coeff_set10_pre2 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [30:24] RW/V |
affe_coeff_set10_post2 Reset: hex:0x00; |
| [22:16] RW/V |
affe_coeff_set10_post1 Reset: hex:0x00; |
| [14:08] RW/V |
affe_coeff_set10_pre1 Reset: hex:0x00; |
| [06:00] RW/V |
affe_coeff_set10_pre2 Reset: hex:0x00; |
+0x000007c0 Register(32 bit) affe_lms_set11
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7c0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x80808080 | ||
| Undefined | 0x80808080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_coeff_set11_post2 | - | affe_coeff_set11_post1 | - | affe_coeff_set11_pre1 | - | affe_coeff_set11_pre2 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [30:24] RW/V |
affe_coeff_set11_post2 Reset: hex:0x00; |
| [22:16] RW/V |
affe_coeff_set11_post1 Reset: hex:0x00; |
| [14:08] RW/V |
affe_coeff_set11_pre1 Reset: hex:0x00; |
| [06:00] RW/V |
affe_coeff_set11_pre2 Reset: hex:0x00; |
+0x000007c4 Register(32 bit) affe_lms_set12
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7c4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x80808080 | ||
| Undefined | 0x80808080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_coeff_set12_post2 | - | affe_coeff_set12_post1 | - | affe_coeff_set12_pre1 | - | affe_coeff_set12_pre2 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [30:24] RW/V |
affe_coeff_set12_post2 Reset: hex:0x00; |
| [22:16] RW/V |
affe_coeff_set12_post1 Reset: hex:0x00; |
| [14:08] RW/V |
affe_coeff_set12_pre1 Reset: hex:0x00; |
| [06:00] RW/V |
affe_coeff_set12_pre2 Reset: hex:0x00; |
+0x000007c8 Register(32 bit) affe_lms_set13
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7c8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x80808080 | ||
| Undefined | 0x80808080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_coeff_set13_post2 | - | affe_coeff_set13_post1 | - | affe_coeff_set13_pre1 | - | affe_coeff_set13_pre2 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [30:24] RW/V |
affe_coeff_set13_post2 Reset: hex:0x00; |
| [22:16] RW/V |
affe_coeff_set13_post1 Reset: hex:0x00; |
| [14:08] RW/V |
affe_coeff_set13_pre1 Reset: hex:0x00; |
| [06:00] RW/V |
affe_coeff_set13_pre2 Reset: hex:0x00; |
+0x000007cc Register(32 bit) affe_lms_set14
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7cc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x80808080 | ||
| Undefined | 0x80808080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_coeff_set14_post2 | - | affe_coeff_set14_post1 | - | affe_coeff_set14_pre1 | - | affe_coeff_set14_pre2 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [30:24] RW/V |
affe_coeff_set14_post2 Reset: hex:0x00; |
| [22:16] RW/V |
affe_coeff_set14_post1 Reset: hex:0x00; |
| [14:08] RW/V |
affe_coeff_set14_pre1 Reset: hex:0x00; |
| [06:00] RW/V |
affe_coeff_set14_pre2 Reset: hex:0x00; |
+0x000007d0 Register(32 bit) affe_lms_set15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7d0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x80808080 | ||
| Undefined | 0x80808080 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | affe_coeff_set15_post2 | - | affe_coeff_set15_post1 | - | affe_coeff_set15_pre1 | - | affe_coeff_set15_pre2 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [30:24] RW/V |
affe_coeff_set15_post2 Reset: hex:0x00; |
| [22:16] RW/V |
affe_coeff_set15_post1 Reset: hex:0x00; |
| [14:08] RW/V |
affe_coeff_set15_pre1 Reset: hex:0x00; |
| [06:00] RW/V |
affe_coeff_set15_pre2 Reset: hex:0x00; |
+0x000007d4 Register(32 bit) affe_lms_frac_set0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7d4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | affe_coeff_set0_frac_post2 | affe_coeff_set0_frac_post1 | affe_coeff_set0_frac_pre1 | affe_coeff_set0_frac_pre2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
affe_coeff_set0_frac_post2 Reset: hex:0x00; |
| [23:16] RW/V |
affe_coeff_set0_frac_post1 Reset: hex:0x00; |
| [15:08] RW/V |
affe_coeff_set0_frac_pre1 Reset: hex:0x00; |
| [07:00] RW/V |
affe_coeff_set0_frac_pre2 Reset: hex:0x00; |
+0x000007d8 Register(32 bit) affe_lms_frac_set1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7d8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | affe_coeff_set1_frac_post2 | affe_coeff_set1_frac_post1 | affe_coeff_set1_frac_pre1 | affe_coeff_set1_frac_pre2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
affe_coeff_set1_frac_post2 Reset: hex:0x00; |
| [23:16] RW/V |
affe_coeff_set1_frac_post1 Reset: hex:0x00; |
| [15:08] RW/V |
affe_coeff_set1_frac_pre1 Reset: hex:0x00; |
| [07:00] RW/V |
affe_coeff_set1_frac_pre2 Reset: hex:0x00; |
+0x000007dc Register(32 bit) affe_lms_frac_set2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7dc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | affe_coeff_set2_frac_post2 | affe_coeff_set2_frac_post1 | affe_coeff_set2_frac_pre1 | affe_coeff_set2_frac_pre2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
affe_coeff_set2_frac_post2 Reset: hex:0x00; |
| [23:16] RW/V |
affe_coeff_set2_frac_post1 Reset: hex:0x00; |
| [15:08] RW/V |
affe_coeff_set2_frac_pre1 Reset: hex:0x00; |
| [07:00] RW/V |
affe_coeff_set2_frac_pre2 Reset: hex:0x00; |
+0x000007e0 Register(32 bit) affe_lms_frac_set3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7e0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | affe_coeff_set3_frac_post2 | affe_coeff_set3_frac_post1 | affe_coeff_set3_frac_pre1 | affe_coeff_set3_frac_pre2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
affe_coeff_set3_frac_post2 Reset: hex:0x00; |
| [23:16] RW/V |
affe_coeff_set3_frac_post1 Reset: hex:0x00; |
| [15:08] RW/V |
affe_coeff_set3_frac_pre1 Reset: hex:0x00; |
| [07:00] RW/V |
affe_coeff_set3_frac_pre2 Reset: hex:0x00; |
+0x000007e4 Register(32 bit) affe_lms_frac_set4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7e4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | affe_coeff_set4_frac_post2 | affe_coeff_set4_frac_post1 | affe_coeff_set4_frac_pre1 | affe_coeff_set4_frac_pre2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
affe_coeff_set4_frac_post2 Reset: hex:0x00; |
| [23:16] RW/V |
affe_coeff_set4_frac_post1 Reset: hex:0x00; |
| [15:08] RW/V |
affe_coeff_set4_frac_pre1 Reset: hex:0x00; |
| [07:00] RW/V |
affe_coeff_set4_frac_pre2 Reset: hex:0x00; |
+0x000007e8 Register(32 bit) affe_lms_frac_set5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7e8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | affe_coeff_set5_frac_post2 | affe_coeff_set5_frac_post1 | affe_coeff_set5_frac_pre1 | affe_coeff_set5_frac_pre2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
affe_coeff_set5_frac_post2 Reset: hex:0x00; |
| [23:16] RW/V |
affe_coeff_set5_frac_post1 Reset: hex:0x00; |
| [15:08] RW/V |
affe_coeff_set5_frac_pre1 Reset: hex:0x00; |
| [07:00] RW/V |
affe_coeff_set5_frac_pre2 Reset: hex:0x00; |
+0x000007ec Register(32 bit) affe_lms_frac_set6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7ec at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | affe_coeff_set6_frac_post2 | affe_coeff_set6_frac_post1 | affe_coeff_set6_frac_pre1 | affe_coeff_set6_frac_pre2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
affe_coeff_set6_frac_post2 Reset: hex:0x00; |
| [23:16] RW/V |
affe_coeff_set6_frac_post1 Reset: hex:0x00; |
| [15:08] RW/V |
affe_coeff_set6_frac_pre1 Reset: hex:0x00; |
| [07:00] RW/V |
affe_coeff_set6_frac_pre2 Reset: hex:0x00; |
+0x000007f0 Register(32 bit) affe_lms_frac_set7
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7f0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | affe_coeff_set7_frac_post2 | affe_coeff_set7_frac_post1 | affe_coeff_set7_frac_pre1 | affe_coeff_set7_frac_pre2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
affe_coeff_set7_frac_post2 Reset: hex:0x00; |
| [23:16] RW/V |
affe_coeff_set7_frac_post1 Reset: hex:0x00; |
| [15:08] RW/V |
affe_coeff_set7_frac_pre1 Reset: hex:0x00; |
| [07:00] RW/V |
affe_coeff_set7_frac_pre2 Reset: hex:0x00; |
+0x000007f4 Register(32 bit) affe_lms_frac_set8
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7f4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | affe_coeff_set8_frac_post2 | affe_coeff_set8_frac_post1 | affe_coeff_set8_frac_pre1 | affe_coeff_set8_frac_pre2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
affe_coeff_set8_frac_post2 Reset: hex:0x00; |
| [23:16] RW/V |
affe_coeff_set8_frac_post1 Reset: hex:0x00; |
| [15:08] RW/V |
affe_coeff_set8_frac_pre1 Reset: hex:0x00; |
| [07:00] RW/V |
affe_coeff_set8_frac_pre2 Reset: hex:0x00; |
+0x000007f8 Register(32 bit) affe_lms_frac_set9
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7f8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | affe_coeff_set9_frac_post2 | affe_coeff_set9_frac_post1 | affe_coeff_set9_frac_pre1 | affe_coeff_set9_frac_pre2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
affe_coeff_set9_frac_post2 Reset: hex:0x00; |
| [23:16] RW/V |
affe_coeff_set9_frac_post1 Reset: hex:0x00; |
| [15:08] RW/V |
affe_coeff_set9_frac_pre1 Reset: hex:0x00; |
| [07:00] RW/V |
affe_coeff_set9_frac_pre2 Reset: hex:0x00; |
+0x000007fc Register(32 bit) affe_lms_frac_set10
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e7fc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | affe_coeff_set10_frac_post2 | affe_coeff_set10_frac_post1 | affe_coeff_set10_frac_pre1 | affe_coeff_set10_frac_pre2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
affe_coeff_set10_frac_post2 Reset: hex:0x00; |
| [23:16] RW/V |
affe_coeff_set10_frac_post1 Reset: hex:0x00; |
| [15:08] RW/V |
affe_coeff_set10_frac_pre1 Reset: hex:0x00; |
| [07:00] RW/V |
affe_coeff_set10_frac_pre2 Reset: hex:0x00; |
+0x00000800 Register(32 bit) affe_lms_frac_set11
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e800 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | affe_coeff_set11_frac_post2 | affe_coeff_set11_frac_post1 | affe_coeff_set11_frac_pre1 | affe_coeff_set11_frac_pre2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
affe_coeff_set11_frac_post2 Reset: hex:0x00; |
| [23:16] RW/V |
affe_coeff_set11_frac_post1 Reset: hex:0x00; |
| [15:08] RW/V |
affe_coeff_set11_frac_pre1 Reset: hex:0x00; |
| [07:00] RW/V |
affe_coeff_set11_frac_pre2 Reset: hex:0x00; |
+0x00000804 Register(32 bit) affe_lms_frac_set12
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e804 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | affe_coeff_set12_frac_post2 | affe_coeff_set12_frac_post1 | affe_coeff_set12_frac_pre1 | affe_coeff_set12_frac_pre2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
affe_coeff_set12_frac_post2 Reset: hex:0x00; |
| [23:16] RW/V |
affe_coeff_set12_frac_post1 Reset: hex:0x00; |
| [15:08] RW/V |
affe_coeff_set12_frac_pre1 Reset: hex:0x00; |
| [07:00] RW/V |
affe_coeff_set12_frac_pre2 Reset: hex:0x00; |
+0x00000808 Register(32 bit) affe_lms_frac_set13
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e808 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | affe_coeff_set13_frac_post2 | affe_coeff_set13_frac_post1 | affe_coeff_set13_frac_pre1 | affe_coeff_set13_frac_pre2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
affe_coeff_set13_frac_post2 Reset: hex:0x00; |
| [23:16] RW/V |
affe_coeff_set13_frac_post1 Reset: hex:0x00; |
| [15:08] RW/V |
affe_coeff_set13_frac_pre1 Reset: hex:0x00; |
| [07:00] RW/V |
affe_coeff_set13_frac_pre2 Reset: hex:0x00; |
+0x0000080c Register(32 bit) affe_lms_frac_set14
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e80c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | affe_coeff_set14_frac_post2 | affe_coeff_set14_frac_post1 | affe_coeff_set14_frac_pre1 | affe_coeff_set14_frac_pre2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
affe_coeff_set14_frac_post2 Reset: hex:0x00; |
| [23:16] RW/V |
affe_coeff_set14_frac_post1 Reset: hex:0x00; |
| [15:08] RW/V |
affe_coeff_set14_frac_pre1 Reset: hex:0x00; |
| [07:00] RW/V |
affe_coeff_set14_frac_pre2 Reset: hex:0x00; |
+0x00000810 Register(32 bit) affe_lms_frac_set15
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e810 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | affe_coeff_set15_frac_post2 | affe_coeff_set15_frac_post1 | affe_coeff_set15_frac_pre1 | affe_coeff_set15_frac_pre2 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
affe_coeff_set15_frac_post2 Reset: hex:0x00; |
| [23:16] RW/V |
affe_coeff_set15_frac_post1 Reset: hex:0x00; |
| [15:08] RW/V |
affe_coeff_set15_frac_pre1 Reset: hex:0x00; |
| [07:00] RW/V |
affe_coeff_set15_frac_pre2 Reset: hex:0x00; |
+0x00000814 Register(32 bit) saturation_status_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e814 at NOC.jesd__axi (Mem)
Access RO/C/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_bankC_float3_sat | ffe_bankC_float2_sat | ffe_bankC_float1_sat | ffe_bankB_float3_sat | ffe_bankB_float2_sat | ffe_bankB_float1_sat | ffe_bankA_float3_sat | ffe_bankA_float2_sat | ffe_bankA_float1_sat | ffe_post_12_sat | ffe_post_11_sat | ffe_post_10_sat | ffe_post_9_sat | ffe_post_8_sat | ffe_post_7_sat | ffe_post_6_sat | ffe_post_5_sat | ffe_post_4_sat | ffe_post_3_sat | ffe_post_2_sat | ffe_post_1_sat | ffe_pre_1_sat | ffe_pre_2_sat | ffe_pre_3_sat | vref_adc_3_sat | vref_adc_2_sat | vref_adc_1_sat | vref_adc_0_sat | vref_ffe_3_sat | vref_ffe_2_sat | vref_ffe_1_sat | vref_ffe_0_sat |
| Access | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V |
| [31:31] RO/C/V |
ffe_bankC_float3_sat Reset: hex:0x0; |
| [30:30] RO/C/V |
ffe_bankC_float2_sat Reset: hex:0x0; |
| [29:29] RO/C/V |
ffe_bankC_float1_sat Reset: hex:0x0; |
| [28:28] RO/C/V |
ffe_bankB_float3_sat Reset: hex:0x0; |
| [27:27] RO/C/V |
ffe_bankB_float2_sat Reset: hex:0x0; |
| [26:26] RO/C/V |
ffe_bankB_float1_sat Reset: hex:0x0; |
| [25:25] RO/C/V |
ffe_bankA_float3_sat Reset: hex:0x0; |
| [24:24] RO/C/V |
ffe_bankA_float2_sat Reset: hex:0x0; |
| [23:23] RO/C/V |
ffe_bankA_float1_sat Reset: hex:0x0; |
| [22:22] RO/C/V |
ffe_post_12_sat Reset: hex:0x0; |
| [21:21] RO/C/V |
ffe_post_11_sat Reset: hex:0x0; |
| [20:20] RO/C/V |
ffe_post_10_sat Reset: hex:0x0; |
| [19:19] RO/C/V |
ffe_post_9_sat Reset: hex:0x0; |
| [18:18] RO/C/V |
ffe_post_8_sat Reset: hex:0x0; |
| [17:17] RO/C/V |
ffe_post_7_sat Reset: hex:0x0; |
| [16:16] RO/C/V |
ffe_post_6_sat Reset: hex:0x0; |
| [15:15] RO/C/V |
ffe_post_5_sat Reset: hex:0x0; |
| [14:14] RO/C/V |
ffe_post_4_sat Reset: hex:0x0; |
| [13:13] RO/C/V |
ffe_post_3_sat Reset: hex:0x0; |
| [12:12] RO/C/V |
ffe_post_2_sat Reset: hex:0x0; |
| [11:11] RO/C/V |
ffe_post_1_sat Reset: hex:0x0; |
| [10:10] RO/C/V |
ffe_pre_1_sat Reset: hex:0x0; |
| [09:09] RO/C/V |
ffe_pre_2_sat Reset: hex:0x0; |
| [08:08] RO/C/V |
ffe_pre_3_sat Reset: hex:0x0; |
| [07:07] RO/C/V |
vref_adc_3_sat Reset: hex:0x0; |
| [06:06] RO/C/V |
vref_adc_2_sat Reset: hex:0x0; |
| [05:05] RO/C/V |
vref_adc_1_sat Reset: hex:0x0; |
| [04:04] RO/C/V |
vref_adc_0_sat Reset: hex:0x0; |
| [03:03] RO/C/V |
vref_ffe_3_sat Reset: hex:0x0; |
| [02:02] RO/C/V |
vref_ffe_2_sat Reset: hex:0x0; |
| [01:01] RO/C/V |
vref_ffe_1_sat Reset: hex:0x0; |
| [00:00] RO/C/V |
vref_ffe_0_sat Reset: hex:0x0; |
+0x00000818 Register(32 bit) saturation_status_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e818 at NOC.jesd__axi (Mem)
Access RO/C/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xffffff00 | ||
| Undefined | 0xffffff00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ops_taps_7_sat | ops_taps_6_sat | ops_taps_5_sat | ops_taps_4_sat | ops_taps_3_sat | ops_taps_2_sat | ops_taps_1_sat | ops_taps_0_sat | |||||||||||||||||||||||
| Access | - | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | |||||||||||||||||||||||
| [07:07] RO/C/V |
ops_taps_7_sat Reset: hex:0x0; |
| [06:06] RO/C/V |
ops_taps_6_sat Reset: hex:0x0; |
| [05:05] RO/C/V |
ops_taps_5_sat Reset: hex:0x0; |
| [04:04] RO/C/V |
ops_taps_4_sat Reset: hex:0x0; |
| [03:03] RO/C/V |
ops_taps_3_sat Reset: hex:0x0; |
| [02:02] RO/C/V |
ops_taps_2_sat Reset: hex:0x0; |
| [01:01] RO/C/V |
ops_taps_1_sat Reset: hex:0x0; |
| [00:00] RO/C/V |
ops_taps_0_sat Reset: hex:0x0; |
+0x00000820 Register(32 bit) saturation_status_3
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e820 at NOC.jesd__axi (Mem)
Access RO/C/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0x08000000 | ||
| Undefined | 0x08000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_vref_3_sat | cdr_ffe_vref_2_sat | cdr_ffe_vref_1_sat | cdr_ffe_vref_0_sat | - | cdr_ffe_ofc_lol_sat | cdr_ffe_ofc_lor_sat | cdr_ffe_ofc_zrl_sat | cdr_ffe_ofc_zrr_sat | cdr_ffe_ofc_hil_sat | cdr_ffe_ofc_hir_sat | dfe_sat | ofc_lol_sat | ofc_lor_sat | ofc_zrl_sat | ofc_zrr_sat | ofc_hil_sat | ofc_hir_sat | adcofc_lol_sat | adcofc_lor_sat | adcofc_zrl_sat | adcofc_zrr_sat | adcofc_hil_sat | adcofc_hir_sat | vga_tap_sat | affe_post2_sat | affe_post1_sat | affe_pre1_sat | affe_pre2_sat | edgvref_lo_sat | edgvref_zr_sat | edgvref_hi_sat |
| Access | RO/C/V | RO/C/V | RO/C/V | RO/C/V | - | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V |
| [31:31] RO/C/V |
cdr_ffe_vref_3_sat Reset: hex:0x0; |
| [30:30] RO/C/V |
cdr_ffe_vref_2_sat Reset: hex:0x0; |
| [29:29] RO/C/V |
cdr_ffe_vref_1_sat Reset: hex:0x0; |
| [28:28] RO/C/V |
cdr_ffe_vref_0_sat Reset: hex:0x0; |
| [26:26] RO/C/V |
cdr_ffe_ofc_lol_sat Reset: hex:0x0; |
| [25:25] RO/C/V |
cdr_ffe_ofc_lor_sat Reset: hex:0x0; |
| [24:24] RO/C/V |
cdr_ffe_ofc_zrl_sat Reset: hex:0x0; |
| [23:23] RO/C/V |
cdr_ffe_ofc_zrr_sat Reset: hex:0x0; |
| [22:22] RO/C/V |
cdr_ffe_ofc_hil_sat Reset: hex:0x0; |
| [21:21] RO/C/V |
cdr_ffe_ofc_hir_sat Reset: hex:0x0; |
| [20:20] RO/C/V |
dfe_sat Reset: hex:0x0; |
| [19:19] RO/C/V |
ofc_lol_sat Reset: hex:0x0; |
| [18:18] RO/C/V |
ofc_lor_sat Reset: hex:0x0; |
| [17:17] RO/C/V |
ofc_zrl_sat Reset: hex:0x0; |
| [16:16] RO/C/V |
ofc_zrr_sat Reset: hex:0x0; |
| [15:15] RO/C/V |
ofc_hil_sat Reset: hex:0x0; |
| [14:14] RO/C/V |
ofc_hir_sat Reset: hex:0x0; |
| [13:13] RO/C/V |
adcofc_lol_sat Reset: hex:0x0; |
| [12:12] RO/C/V |
adcofc_lor_sat Reset: hex:0x0; |
| [11:11] RO/C/V |
adcofc_zrl_sat Reset: hex:0x0; |
| [10:10] RO/C/V |
adcofc_zrr_sat Reset: hex:0x0; |
| [09:09] RO/C/V |
adcofc_hil_sat Reset: hex:0x0; |
| [08:08] RO/C/V |
adcofc_hir_sat Reset: hex:0x0; |
| [07:07] RO/C/V |
vga_tap_sat Reset: hex:0x0; |
| [06:06] RO/C/V |
affe_post2_sat Reset: hex:0x0; |
| [05:05] RO/C/V |
affe_post1_sat Reset: hex:0x0; |
| [04:04] RO/C/V |
affe_pre1_sat Reset: hex:0x0; |
| [03:03] RO/C/V |
affe_pre2_sat Reset: hex:0x0; |
| [02:02] RO/C/V |
edgvref_lo_sat Reset: hex:0x0; |
| [01:01] RO/C/V |
edgvref_zr_sat Reset: hex:0x0; |
| [00:00] RO/C/V |
edgvref_hi_sat Reset: hex:0x0; |
+0x00000824 Register(32 bit) zeroavg_status_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e824 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ffe_bankC_float3_zeroavg | ffe_bankC_float2_zeroavg | ffe_bankC_float1_zeroavg | ffe_bankB_float3_zeroavg | ffe_bankB_float2_zeroavg | ffe_bankB_float1_zeroavg | ffe_bankA_float3_zeroavg | ffe_bankA_float2_zeroavg | ffe_bankA_float1_zeroavg | ffe_post_12_zeroavg | ffe_post_11_zeroavg | ffe_post_10_zeroavg | ffe_post_9_zeroavg | ffe_post_8_zeroavg | ffe_post_7_zeroavg | ffe_post_6_zeroavg | ffe_post_5_zeroavg | ffe_post_4_zeroavg | ffe_post_3_zeroavg | ffe_post_2_zeroavg | ffe_post_1_zeroavg | ffe_pre_1_zeroavg | ffe_pre_2_zeroavg | ffe_pre_3_zeroavg | vref_adc_3_zeroavg | vref_adc_2_zeroavg | vref_adc_1_zeroavg | vref_adc_0_zeroavg | vref_ffe_3_zeroavg | vref_ffe_2_zeroavg | vref_ffe_1_zeroavg | vref_ffe_0_zeroavg |
| Access | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V |
| [31:31] RO/V |
ffe_bankC_float3_zeroavg Reset: hex:0x0; |
| [30:30] RO/V |
ffe_bankC_float2_zeroavg Reset: hex:0x0; |
| [29:29] RO/V |
ffe_bankC_float1_zeroavg Reset: hex:0x0; |
| [28:28] RO/V |
ffe_bankB_float3_zeroavg Reset: hex:0x0; |
| [27:27] RO/V |
ffe_bankB_float2_zeroavg Reset: hex:0x0; |
| [26:26] RO/V |
ffe_bankB_float1_zeroavg Reset: hex:0x0; |
| [25:25] RO/V |
ffe_bankA_float3_zeroavg Reset: hex:0x0; |
| [24:24] RO/V |
ffe_bankA_float2_zeroavg Reset: hex:0x0; |
| [23:23] RO/V |
ffe_bankA_float1_zeroavg Reset: hex:0x0; |
| [22:22] RO/V |
ffe_post_12_zeroavg Reset: hex:0x0; |
| [21:21] RO/V |
ffe_post_11_zeroavg Reset: hex:0x0; |
| [20:20] RO/V |
ffe_post_10_zeroavg Reset: hex:0x0; |
| [19:19] RO/V |
ffe_post_9_zeroavg Reset: hex:0x0; |
| [18:18] RO/V |
ffe_post_8_zeroavg Reset: hex:0x0; |
| [17:17] RO/V |
ffe_post_7_zeroavg Reset: hex:0x0; |
| [16:16] RO/V |
ffe_post_6_zeroavg Reset: hex:0x0; |
| [15:15] RO/V |
ffe_post_5_zeroavg Reset: hex:0x0; |
| [14:14] RO/V |
ffe_post_4_zeroavg Reset: hex:0x0; |
| [13:13] RO/V |
ffe_post_3_zeroavg Reset: hex:0x0; |
| [12:12] RO/V |
ffe_post_2_zeroavg Reset: hex:0x0; |
| [11:11] RO/V |
ffe_post_1_zeroavg Reset: hex:0x0; |
| [10:10] RO/V |
ffe_pre_1_zeroavg Reset: hex:0x0; |
| [09:09] RO/V |
ffe_pre_2_zeroavg Reset: hex:0x0; |
| [08:08] RO/V |
ffe_pre_3_zeroavg Reset: hex:0x0; |
| [07:07] RO/V |
vref_adc_3_zeroavg Reset: hex:0x0; |
| [06:06] RO/V |
vref_adc_2_zeroavg Reset: hex:0x0; |
| [05:05] RO/V |
vref_adc_1_zeroavg Reset: hex:0x0; |
| [04:04] RO/V |
vref_adc_0_zeroavg Reset: hex:0x0; |
| [03:03] RO/V |
vref_ffe_3_zeroavg Reset: hex:0x0; |
| [02:02] RO/V |
vref_ffe_2_zeroavg Reset: hex:0x0; |
| [01:01] RO/V |
vref_ffe_1_zeroavg Reset: hex:0x0; |
| [00:00] RO/V |
vref_ffe_0_zeroavg Reset: hex:0x0; |
+0x00000828 Register(32 bit) zeroavg_status_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e828 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xffffff00 | ||
| Undefined | 0xffffff00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ops_taps_zeroavg | ||||||||||||||||||||||||||||||
| Access | - | RO/V | ||||||||||||||||||||||||||||||
| [07:00] RO/V |
ops_taps_zeroavg Reset: hex:0x00; |
+0x00000830 Register(32 bit) zeroavg_status_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e830 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfff00000 | ||
| Undefined | 0xfff00000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | dfe_zeroavg | cdr_ffe_zeroavg | cdr_ffe_vref_zeroavg | vga_tap_zeroavg | affe_post2_zeroavg | affe_post1_zeroavg | affe_pre1_zeroavg | affe_pre2_zeroavg | edgvref_lo_zeroavg | edgvref_zr_zeroavg | edgvref_hi_zeroavg | ||||||||||||||||||||
| Access | - | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | ||||||||||||||||||||
| [19:19] RO/V |
dfe_zeroavg Reset: hex:0x0; |
| [18:12] RO/V |
cdr_ffe_zeroavg Reset: hex:0x00; |
| [11:08] RO/V |
cdr_ffe_vref_zeroavg Reset: hex:0x0; |
| [07:07] RO/V |
vga_tap_zeroavg Reset: hex:0x0; |
| [06:06] RO/V |
affe_post2_zeroavg Reset: hex:0x0; |
| [05:05] RO/V |
affe_post1_zeroavg Reset: hex:0x0; |
| [04:04] RO/V |
affe_pre1_zeroavg Reset: hex:0x0; |
| [03:03] RO/V |
affe_pre2_zeroavg Reset: hex:0x0; |
| [02:02] RO/V |
edgvref_lo_zeroavg Reset: hex:0x0; |
| [01:01] RO/V |
edgvref_zr_zeroavg Reset: hex:0x0; |
| [00:00] RO/V |
edgvref_hi_zeroavg Reset: hex:0x0; |
+0x00000834 Register(32 bit) adcofc_control_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e834 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00010020 | |
| Unaffected | 0xf0380000 | ||
| Undefined | 0xf0380000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| Name | - | adcofc_hold_en | - | adcofc_stats_max | adcofc_timer_max | adcofc_updn_inv_cb | ||||||||||||||||||||||||||
| Access | - | RW | - | RW | RW | RW | ||||||||||||||||||||||||||
| [27:22] RW |
adcofc_hold_en Reset: hex:0x00; |
| [18:09] RW |
adcofc_stats_max Reset: hex:0x080; |
| [08:01] RW |
adcofc_timer_max Reset: hex:0x10; |
| [00:00] RW |
adcofc_updn_inv_cb Reset: hex:0x0; |
+0x00000838 Register(32 bit) adcofc_control_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e838 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00002d2d | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 0 | 1 | 1 | 0 | 1 | - | - | 1 | 0 | 1 | 1 | 0 | 1 |
| Name | - | adcofc_init_val_3 | - | adcofc_init_val_2 | - | adcofc_init_val_1 | - | adcofc_init_val_0 | ||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | - | RW | ||||||||||||||||||||||||
| [29:24] RW |
adcofc_init_val_3 Reset: hex:0x00; |
| [21:16] RW |
adcofc_init_val_2 Reset: hex:0x00; |
| [13:08] RW |
adcofc_init_val_1 Reset: hex:0x2d; |
| [05:00] RW |
adcofc_init_val_0 Reset: hex:0x2d; |
+0x0000083c Register(32 bit) adcofc_control_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e83c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x4d310410 | |
| Unaffected | 0x000e0000 | ||
| Undefined | 0x000e0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | adcofc_init_val_5 | adcofc_init_val_4 | - | adcofc_coarse_mu_en | adcofc_mu_fine | adcofc_mu_coarse | ||||||||||||||||||||||||||
| Access | RW | RW | - | RW | RW | RW | ||||||||||||||||||||||||||
| [31:26] RW |
adcofc_init_val_5 Reset: hex:0x13; |
| [25:20] RW |
adcofc_init_val_4 Reset: hex:0x13; |
| [16:16] RW |
adcofc_coarse_mu_en Reset: hex:0x1; |
| [15:08] RW |
adcofc_mu_fine Reset: hex:0x04; |
| [07:00] RW |
adcofc_mu_coarse Reset: hex:0x10; |
+0x00000840 Register(32 bit) adcofc_control_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e840 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0000081f | |
| Unaffected | 0xfffff000 | ||
| Undefined | 0xfffff000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | adcofc_tap_min | adcofc_tap_max | |||||||||||||||||||||||||||||
| Access | - | RW | RW | |||||||||||||||||||||||||||||
| [11:06] RW |
adcofc_tap_min Reset: hex:0x20; |
| [05:00] RW |
adcofc_tap_max Reset: hex:0x1f; |
+0x00000844 Register(32 bit) adcofc_status_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e844 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | adcofc_tap_zr | - | adcofc_tap_lo | - | adcofc_tap_hi | ||||||||||||||||||||||||||
| Access | - | RO/V | - | RO/V | - | RO/V | ||||||||||||||||||||||||||
| [21:16] RO/V |
adcofc_tap_zr Reset: hex:0x00; |
| [13:08] RO/V |
adcofc_tap_lo Reset: hex:0x00; |
| [05:00] RO/V |
adcofc_tap_hi Reset: hex:0x00; |
+0x00000848 Register(32 bit) edg_slice_control_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e848 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000230 | |
| Unaffected | 0xffffe000 | ||
| Undefined | 0xffffe000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| Name | - | edg_slice_inv_err | edg_slice_delay_pgm_sel | edg_slice_delay_val | pd_src_sel | edg_slice_level_src_sel | ||||||||||||||||||||||||||
| Access | - | RW | RW | RW | RW | RW | ||||||||||||||||||||||||||
| [12:12] RW |
edg_slice_inv_err Reset: hex:0x0; |
| [11:11] RW |
edg_slice_delay_pgm_sel Reset: hex:0x0; |
| [10:04] RW |
edg_slice_delay_val Reset: hex:0x23; |
| [03:02] RW |
pd_src_sel Reset: hex:0x0; |
| [01:00] RW |
edg_slice_level_src_sel Reset: hex:0x0; |
+0x0000084c Register(32 bit) edg_slicer_level_set0_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e84c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00300010 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 1 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | edg_slice_level_set0_lo | - | edg_slice_level_set0_zr | - | edg_slice_level_set0_hi | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
edg_slice_level_set0_lo Reset: hex:0x30; |
| [13:08] RW/V |
edg_slice_level_set0_zr Reset: hex:0x00; |
| [05:00] RW/V |
edg_slice_level_set0_hi Reset: hex:0x10; |
+0x00000850 Register(32 bit) edg_slicer_level_set1_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e850 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00300010 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 1 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | edg_slice_level_set1_lo | - | edg_slice_level_set1_zr | - | edg_slice_level_set1_hi | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
edg_slice_level_set1_lo Reset: hex:0x30; |
| [13:08] RW/V |
edg_slice_level_set1_zr Reset: hex:0x00; |
| [05:00] RW/V |
edg_slice_level_set1_hi Reset: hex:0x10; |
+0x00000854 Register(32 bit) edg_slicer_level_set2_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e854 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00300010 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 1 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | edg_slice_level_set2_lo | - | edg_slice_level_set2_zr | - | edg_slice_level_set2_hi | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
edg_slice_level_set2_lo Reset: hex:0x30; |
| [13:08] RW/V |
edg_slice_level_set2_zr Reset: hex:0x00; |
| [05:00] RW/V |
edg_slice_level_set2_hi Reset: hex:0x10; |
+0x00000858 Register(32 bit) edg_slicer_level_set3_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e858 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00300010 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 1 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | edg_slice_level_set3_lo | - | edg_slice_level_set3_zr | - | edg_slice_level_set3_hi | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
edg_slice_level_set3_lo Reset: hex:0x30; |
| [13:08] RW/V |
edg_slice_level_set3_zr Reset: hex:0x00; |
| [05:00] RW/V |
edg_slice_level_set3_hi Reset: hex:0x10; |
+0x0000085c Register(32 bit) edg_slicer_level_set4_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e85c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00300010 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 1 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | edg_slice_level_set4_lo | - | edg_slice_level_set4_zr | - | edg_slice_level_set4_hi | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
edg_slice_level_set4_lo Reset: hex:0x30; |
| [13:08] RW/V |
edg_slice_level_set4_zr Reset: hex:0x00; |
| [05:00] RW/V |
edg_slice_level_set4_hi Reset: hex:0x10; |
+0x00000860 Register(32 bit) edg_slicer_level_set5_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e860 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00300010 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 1 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | edg_slice_level_set5_lo | - | edg_slice_level_set5_zr | - | edg_slice_level_set5_hi | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
edg_slice_level_set5_lo Reset: hex:0x30; |
| [13:08] RW/V |
edg_slice_level_set5_zr Reset: hex:0x00; |
| [05:00] RW/V |
edg_slice_level_set5_hi Reset: hex:0x10; |
+0x00000864 Register(32 bit) edg_slicer_level_set6_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e864 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00300010 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 1 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | edg_slice_level_set6_lo | - | edg_slice_level_set6_zr | - | edg_slice_level_set6_hi | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
edg_slice_level_set6_lo Reset: hex:0x30; |
| [13:08] RW/V |
edg_slice_level_set6_zr Reset: hex:0x00; |
| [05:00] RW/V |
edg_slice_level_set6_hi Reset: hex:0x10; |
+0x00000868 Register(32 bit) edg_slicer_level_set7_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e868 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00300010 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 1 | 1 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | edg_slice_level_set7_lo | - | edg_slice_level_set7_zr | - | edg_slice_level_set7_hi | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
edg_slice_level_set7_lo Reset: hex:0x30; |
| [13:08] RW/V |
edg_slice_level_set7_zr Reset: hex:0x00; |
| [05:00] RW/V |
edg_slice_level_set7_hi Reset: hex:0x10; |
+0x0000086c Register(32 bit) edgvref_control_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e86c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000100 | |
| Unaffected | 0xfffffe00 | ||
| Undefined | 0xfffffe00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | edgvref_int_iter_bypass | edgvref_int_iter_max | edgvref_updn_inv_cb | edgvref_hold_en | |||||||||||||||||||||||||||
| Access | - | RW | RW | RW | RW | |||||||||||||||||||||||||||
| [08:08] RW |
edgvref_int_iter_bypass Reset: hex:0x1; |
| [07:04] RW |
edgvref_int_iter_max Reset: hex:0x0; |
| [03:03] RW |
edgvref_updn_inv_cb Reset: hex:0x0; |
| [02:00] RW |
edgvref_hold_en Reset: hex:0x0; |
+0x00000870 Register(32 bit) edgvref_control_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e870 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0000002d | |
| Unaffected | 0xffffc0c0 | ||
| Undefined | 0xffffc0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 0 | 1 | 1 | 0 | 1 |
| Name | - | edgvref_init_val_1 | - | edgvref_init_val_0 | ||||||||||||||||||||||||||||
| Access | - | RW | - | RW | ||||||||||||||||||||||||||||
| [13:08] RW |
edgvref_init_val_1 Reset: hex:0x00; |
| [05:00] RW |
edgvref_init_val_0 Reset: hex:0x2d; |
+0x00000874 Register(32 bit) edgvref_control_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e874 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000013 | |
| Unaffected | 0xffffffc0 | ||
| Undefined | 0xffffffc0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 0 | 0 | 1 | 1 |
| Name | - | edgvref_init_val_2 | ||||||||||||||||||||||||||||||
| Access | - | RW | ||||||||||||||||||||||||||||||
| [05:00] RW |
edgvref_init_val_2 Reset: hex:0x13; |
+0x00000878 Register(32 bit) edgvref_control_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e878 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00004008 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| Name | - | edgvref_stats_max | edgvref_timer_max | |||||||||||||||||||||||||||||
| Access | - | RW | RW | |||||||||||||||||||||||||||||
| [17:08] RW |
edgvref_stats_max Reset: hex:0x040; |
| [07:00] RW |
edgvref_timer_max Reset: hex:0x08; |
+0x0000087c Register(32 bit) edgvref_control_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e87c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0000201f | |
| Unaffected | 0xffffc0c0 | ||
| Undefined | 0xffffc0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | edgvref_tap_min | - | edgvref_tap_max | ||||||||||||||||||||||||||||
| Access | - | RW | - | RW | ||||||||||||||||||||||||||||
| [13:08] RW |
edgvref_tap_min Reset: hex:0x20; |
| [05:00] RW |
edgvref_tap_max Reset: hex:0x1f; |
+0x00000880 Register(32 bit) edgvref_control_6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e880 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000811 | |
| Unaffected | 0xfffc0200 | ||
| Undefined | 0xfffc0200 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | - | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
| Name | - | edgvref_mu_fine | - | edgvref_mu_coarse | edgvref_coarse_mu_en | |||||||||||||||||||||||||||
| Access | - | RW | - | RW | RW | |||||||||||||||||||||||||||
| [17:10] RW |
edgvref_mu_fine Reset: hex:0x02; |
| [08:01] RW |
edgvref_mu_coarse Reset: hex:0x08; |
| [00:00] RW |
edgvref_coarse_mu_en Reset: hex:0x1; |
+0x00000884 Register(32 bit) edgvref_frac_set0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e884 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | edgvref_frac_set0_lo | edgvref_frac_set0_zr | edgvref_frac_set0_hi | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [23:16] RW/V |
edgvref_frac_set0_lo Reset: hex:0x00; |
| [15:08] RW/V |
edgvref_frac_set0_zr Reset: hex:0x00; |
| [07:00] RW/V |
edgvref_frac_set0_hi Reset: hex:0x00; |
+0x00000888 Register(32 bit) edgvref_frac_set1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e888 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | edgvref_frac_set1_lo | edgvref_frac_set1_zr | edgvref_frac_set1_hi | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [23:16] RW/V |
edgvref_frac_set1_lo Reset: hex:0x00; |
| [15:08] RW/V |
edgvref_frac_set1_zr Reset: hex:0x00; |
| [07:00] RW/V |
edgvref_frac_set1_hi Reset: hex:0x00; |
+0x0000088c Register(32 bit) edgvref_frac_set2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e88c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | edgvref_frac_set2_lo | edgvref_frac_set2_zr | edgvref_frac_set2_hi | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [23:16] RW/V |
edgvref_frac_set2_lo Reset: hex:0x00; |
| [15:08] RW/V |
edgvref_frac_set2_zr Reset: hex:0x00; |
| [07:00] RW/V |
edgvref_frac_set2_hi Reset: hex:0x00; |
+0x00000890 Register(32 bit) edgvref_frac_set3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e890 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | edgvref_frac_set3_lo | edgvref_frac_set3_zr | edgvref_frac_set3_hi | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [23:16] RW/V |
edgvref_frac_set3_lo Reset: hex:0x00; |
| [15:08] RW/V |
edgvref_frac_set3_zr Reset: hex:0x00; |
| [07:00] RW/V |
edgvref_frac_set3_hi Reset: hex:0x00; |
+0x00000894 Register(32 bit) edgvref_frac_set4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e894 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | edgvref_frac_set4_lo | edgvref_frac_set4_zr | edgvref_frac_set4_hi | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [23:16] RW/V |
edgvref_frac_set4_lo Reset: hex:0x00; |
| [15:08] RW/V |
edgvref_frac_set4_zr Reset: hex:0x00; |
| [07:00] RW/V |
edgvref_frac_set4_hi Reset: hex:0x00; |
+0x00000898 Register(32 bit) edgvref_frac_set5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e898 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | edgvref_frac_set5_lo | edgvref_frac_set5_zr | edgvref_frac_set5_hi | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [23:16] RW/V |
edgvref_frac_set5_lo Reset: hex:0x00; |
| [15:08] RW/V |
edgvref_frac_set5_zr Reset: hex:0x00; |
| [07:00] RW/V |
edgvref_frac_set5_hi Reset: hex:0x00; |
+0x0000089c Register(32 bit) edgvref_frac_set6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e89c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | edgvref_frac_set6_lo | edgvref_frac_set6_zr | edgvref_frac_set6_hi | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [23:16] RW/V |
edgvref_frac_set6_lo Reset: hex:0x00; |
| [15:08] RW/V |
edgvref_frac_set6_zr Reset: hex:0x00; |
| [07:00] RW/V |
edgvref_frac_set6_hi Reset: hex:0x00; |
+0x000008a0 Register(32 bit) edgvref_frac_set7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8a0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | edgvref_frac_set7_lo | edgvref_frac_set7_zr | edgvref_frac_set7_hi | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [23:16] RW/V |
edgvref_frac_set7_lo Reset: hex:0x00; |
| [15:08] RW/V |
edgvref_frac_set7_zr Reset: hex:0x00; |
| [07:00] RW/V |
edgvref_frac_set7_hi Reset: hex:0x00; |
+0x000008a4 Register(32 bit) jpp_control_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8a4 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000100 | |
| Unaffected | 0xfffe0000 | ||
| Undefined | 0xfffe0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | jpp_dffe_en | jpp_dffe_gain | jpp_dffe_offset | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [16:16] RW |
jpp_dffe_en Reset: hex:0x0; |
| [15:08] RW |
jpp_dffe_gain Reset: hex:0x01; |
| [07:00] RW |
jpp_dffe_offset Reset: hex:0x00; |
+0x000008a8 Register(32 bit) dfe_lms_control_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8a8 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00010020 | |
| Unaffected | 0xfff80000 | ||
| Undefined | 0xfff80000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| Name | - | dfe_stats_max | dfe_timer_max | dfe_updn_inv_cb | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [18:09] RW |
dfe_stats_max Reset: hex:0x080; |
| [08:01] RW |
dfe_timer_max Reset: hex:0x10; |
| [00:00] RW |
dfe_updn_inv_cb Reset: hex:0x0; |
+0x000008ac Register(32 bit) dfe_lms_control_1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8ac at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xffff00fe | ||
| Undefined | 0xffff00fe | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | - | - | - | - | 0 |
| Name | - | dfe_init_val | - | dfe_hold_en | ||||||||||||||||||||||||||||
| Access | - | RW | - | RW | ||||||||||||||||||||||||||||
| [15:08] RW |
dfe_init_val Reset: hex:0x00; |
| [00:00] RW |
dfe_hold_en Reset: hex:0x0; |
+0x000008b0 Register(32 bit) dfe_lms_control_2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8b0 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00010410 | |
| Unaffected | 0xfffe0000 | ||
| Undefined | 0xfffe0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | dfe_coarse_mu_en | dfe_mu_fine | dfe_mu_coarse | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [16:16] RW |
dfe_coarse_mu_en Reset: hex:0x1; |
| [15:08] RW |
dfe_mu_fine Reset: hex:0x04; |
| [07:00] RW |
dfe_mu_coarse Reset: hex:0x10; |
+0x000008b4 Register(32 bit) dfe_lms_control_3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8b4 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0000807f | |
| Unaffected | 0xffff0000 | ||
| Undefined | 0xffff0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Name | - | dfe_tap_min | dfe_tap_max | |||||||||||||||||||||||||||||
| Access | - | RW | RW | |||||||||||||||||||||||||||||
| [15:08] RW |
dfe_tap_min Reset: hex:0x80; |
| [07:00] RW |
dfe_tap_max Reset: hex:0x7f; |
+0x000008b8 Register(32 bit) dfe_lms_status_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8b8 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffffffe | ||
| Undefined | 0xfffffffe | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 |
| Name | - | dfe_avg_updn | ||||||||||||||||||||||||||||||
| Access | - | RO/V | ||||||||||||||||||||||||||||||
| [00:00] RO/V |
dfe_avg_updn Reset: hex:0x0; |
+0x000008bc Register(32 bit) dfe_lms_set0to3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8bc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | dfe_coeff_set3 | dfe_coeff_set2 | dfe_coeff_set1 | dfe_coeff_set0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
dfe_coeff_set3 Reset: hex:0x00; |
| [23:16] RW/V |
dfe_coeff_set2 Reset: hex:0x00; |
| [15:08] RW/V |
dfe_coeff_set1 Reset: hex:0x00; |
| [07:00] RW/V |
dfe_coeff_set0 Reset: hex:0x00; |
+0x000008c0 Register(32 bit) dfe_lms_set4to7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8c0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | dfe_coeff_set7 | dfe_coeff_set6 | dfe_coeff_set5 | dfe_coeff_set4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
dfe_coeff_set7 Reset: hex:0x00; |
| [23:16] RW/V |
dfe_coeff_set6 Reset: hex:0x00; |
| [15:08] RW/V |
dfe_coeff_set5 Reset: hex:0x00; |
| [07:00] RW/V |
dfe_coeff_set4 Reset: hex:0x00; |
+0x000008c4 Register(32 bit) dfe_lms_set8to11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8c4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | dfe_coeff_set11 | dfe_coeff_set10 | dfe_coeff_set9 | dfe_coeff_set8 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
dfe_coeff_set11 Reset: hex:0x00; |
| [23:16] RW/V |
dfe_coeff_set10 Reset: hex:0x00; |
| [15:08] RW/V |
dfe_coeff_set9 Reset: hex:0x00; |
| [07:00] RW/V |
dfe_coeff_set8 Reset: hex:0x00; |
+0x000008c8 Register(32 bit) dfe_lms_set12to15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8c8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | dfe_coeff_set15 | dfe_coeff_set14 | dfe_coeff_set13 | dfe_coeff_set12 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
dfe_coeff_set15 Reset: hex:0x00; |
| [23:16] RW/V |
dfe_coeff_set14 Reset: hex:0x00; |
| [15:08] RW/V |
dfe_coeff_set13 Reset: hex:0x00; |
| [07:00] RW/V |
dfe_coeff_set12 Reset: hex:0x00; |
+0x000008cc Register(32 bit) dfe_lms_frac_set0to3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8cc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | dfe_coeff_set3_frac | dfe_coeff_set2_frac | dfe_coeff_set1_frac | dfe_coeff_set0_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
dfe_coeff_set3_frac Reset: hex:0x00; |
| [23:16] RW/V |
dfe_coeff_set2_frac Reset: hex:0x00; |
| [15:08] RW/V |
dfe_coeff_set1_frac Reset: hex:0x00; |
| [07:00] RW/V |
dfe_coeff_set0_frac Reset: hex:0x00; |
+0x000008d0 Register(32 bit) dfe_lms_frac_set4to7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8d0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | dfe_coeff_set7_frac | dfe_coeff_set6_frac | dfe_coeff_set5_frac | dfe_coeff_set4_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
dfe_coeff_set7_frac Reset: hex:0x00; |
| [23:16] RW/V |
dfe_coeff_set6_frac Reset: hex:0x00; |
| [15:08] RW/V |
dfe_coeff_set5_frac Reset: hex:0x00; |
| [07:00] RW/V |
dfe_coeff_set4_frac Reset: hex:0x00; |
+0x000008d4 Register(32 bit) dfe_lms_frac_set8to11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8d4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | dfe_coeff_set11_frac | dfe_coeff_set10_frac | dfe_coeff_set9_frac | dfe_coeff_set8_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
dfe_coeff_set11_frac Reset: hex:0x00; |
| [23:16] RW/V |
dfe_coeff_set10_frac Reset: hex:0x00; |
| [15:08] RW/V |
dfe_coeff_set9_frac Reset: hex:0x00; |
| [07:00] RW/V |
dfe_coeff_set8_frac Reset: hex:0x00; |
+0x000008d8 Register(32 bit) dfe_lms_frac_set12to15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8d8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | dfe_coeff_set15_frac | dfe_coeff_set14_frac | dfe_coeff_set13_frac | dfe_coeff_set12_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
dfe_coeff_set15_frac Reset: hex:0x00; |
| [23:16] RW/V |
dfe_coeff_set14_frac Reset: hex:0x00; |
| [15:08] RW/V |
dfe_coeff_set13_frac Reset: hex:0x00; |
| [07:00] RW/V |
dfe_coeff_set12_frac Reset: hex:0x00; |
+0x000008dc Register(32 bit) dfe_control_0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8dc at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffffff0 | ||
| Undefined | 0xfffffff0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 |
| Name | - | dfe_opt_sel | dfe_slicer_inv_p_err_cb | dfe_slicer_inv_n_err_cb | dfe_en | |||||||||||||||||||||||||||
| Access | - | RW | RW | RW | RW | |||||||||||||||||||||||||||
| [03:03] RW |
dfe_opt_sel Reset: hex:0x0; |
| [02:02] RW |
dfe_slicer_inv_p_err_cb Reset: hex:0x0; |
| [01:01] RW |
dfe_slicer_inv_n_err_cb Reset: hex:0x0; |
| [00:00] RW |
dfe_en Reset: hex:0x0; |
+0x000008e0 Register(32 bit) rx_sararray_valid_0
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8e0 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | rxdat_sararray_valid_0 | |||||||||||||||||||||||||||||||
| Access | RO/V | |||||||||||||||||||||||||||||||
| [31:00] RO/V |
rxdat_sararray_valid_0 Reset: hex:0x00000000; |
+0x000008e4 Register(32 bit) rx_sararray_valid_1
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8e4 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | rxdat_sararray_valid_1 | |||||||||||||||||||||||||||||||
| Access | RO/V | |||||||||||||||||||||||||||||||
| [31:00] RO/V |
rxdat_sararray_valid_1 Reset: hex:0x00000000; |
+0x000008e8 Register(32 bit) cdr_ffe_pre1_set0to3
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8e8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_pre1_coeff_set3 | cdr_ffe_pre1_coeff_set2 | cdr_ffe_pre1_coeff_set1 | cdr_ffe_pre1_coeff_set0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_pre1_coeff_set3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_pre1_coeff_set2 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_pre1_coeff_set1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_pre1_coeff_set0 Reset: hex:0x00; |
+0x000008ec Register(32 bit) cdr_ffe_pre1_set4to7
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8ec at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_pre1_coeff_set7 | cdr_ffe_pre1_coeff_set6 | cdr_ffe_pre1_coeff_set5 | cdr_ffe_pre1_coeff_set4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_pre1_coeff_set7 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_pre1_coeff_set6 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_pre1_coeff_set5 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_pre1_coeff_set4 Reset: hex:0x00; |
+0x000008f0 Register(32 bit) cdr_ffe_pre1_set8to11
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8f0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_pre1_coeff_set11 | cdr_ffe_pre1_coeff_set10 | cdr_ffe_pre1_coeff_set9 | cdr_ffe_pre1_coeff_set8 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_pre1_coeff_set11 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_pre1_coeff_set10 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_pre1_coeff_set9 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_pre1_coeff_set8 Reset: hex:0x00; |
+0x000008f4 Register(32 bit) cdr_ffe_pre1_set12to15
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8f4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_pre1_coeff_set15 | cdr_ffe_pre1_coeff_set14 | cdr_ffe_pre1_coeff_set13 | cdr_ffe_pre1_coeff_set12 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_pre1_coeff_set15 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_pre1_coeff_set14 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_pre1_coeff_set13 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_pre1_coeff_set12 Reset: hex:0x00; |
+0x000008f8 Register(32 bit) cdr_ffe_slicer_level_set0_control
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8f8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x560000a8 | |
| Unaffected | 0x80200e00 | ||
| Undefined | 0x80200e00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_slice_level_set0_m1 | - | cdr_ffe_slice_level_set0_0 | - | cdr_ffe_slice_level_set0_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [30:22] RW/V |
cdr_ffe_slice_level_set0_m1 Reset: hex:0x158; |
| [20:12] RW/V |
cdr_ffe_slice_level_set0_0 Reset: hex:0x000; |
| [08:00] RW/V |
cdr_ffe_slice_level_set0_p1 Reset: hex:0x0a8; |
+0x000008fc Register(32 bit) cdr_ffe_slicer_level_set1_control
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e8fc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x560000a8 | |
| Unaffected | 0x80200e00 | ||
| Undefined | 0x80200e00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_slice_level_set1_m1 | - | cdr_ffe_slice_level_set1_0 | - | cdr_ffe_slice_level_set1_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [30:22] RW/V |
cdr_ffe_slice_level_set1_m1 Reset: hex:0x158; |
| [20:12] RW/V |
cdr_ffe_slice_level_set1_0 Reset: hex:0x000; |
| [08:00] RW/V |
cdr_ffe_slice_level_set1_p1 Reset: hex:0x0a8; |
+0x00000900 Register(32 bit) cdr_ffe_slicer_level_set2_control
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e900 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x560000a8 | |
| Unaffected | 0x80200e00 | ||
| Undefined | 0x80200e00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_slice_level_set2_m1 | - | cdr_ffe_slice_level_set2_0 | - | cdr_ffe_slice_level_set2_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [30:22] RW/V |
cdr_ffe_slice_level_set2_m1 Reset: hex:0x158; |
| [20:12] RW/V |
cdr_ffe_slice_level_set2_0 Reset: hex:0x000; |
| [08:00] RW/V |
cdr_ffe_slice_level_set2_p1 Reset: hex:0x0a8; |
+0x00000904 Register(32 bit) cdr_ffe_slicer_level_set3_control
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e904 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x560000a8 | |
| Unaffected | 0x80200e00 | ||
| Undefined | 0x80200e00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_slice_level_set3_m1 | - | cdr_ffe_slice_level_set3_0 | - | cdr_ffe_slice_level_set3_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [30:22] RW/V |
cdr_ffe_slice_level_set3_m1 Reset: hex:0x158; |
| [20:12] RW/V |
cdr_ffe_slice_level_set3_0 Reset: hex:0x000; |
| [08:00] RW/V |
cdr_ffe_slice_level_set3_p1 Reset: hex:0x0a8; |
+0x0000090c Register(32 bit) cdr_ffe_slicer_level_set4_control
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e90c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x560000a8 | |
| Unaffected | 0x80200e00 | ||
| Undefined | 0x80200e00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_slice_level_set4_m1 | - | cdr_ffe_slice_level_set4_0 | - | cdr_ffe_slice_level_set4_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [30:22] RW/V |
cdr_ffe_slice_level_set4_m1 Reset: hex:0x158; |
| [20:12] RW/V |
cdr_ffe_slice_level_set4_0 Reset: hex:0x000; |
| [08:00] RW/V |
cdr_ffe_slice_level_set4_p1 Reset: hex:0x0a8; |
+0x00000910 Register(32 bit) cdr_ffe_slicer_level_set5_control
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e910 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x560000a8 | |
| Unaffected | 0x80200e00 | ||
| Undefined | 0x80200e00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_slice_level_set5_m1 | - | cdr_ffe_slice_level_set5_0 | - | cdr_ffe_slice_level_set5_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [30:22] RW/V |
cdr_ffe_slice_level_set5_m1 Reset: hex:0x158; |
| [20:12] RW/V |
cdr_ffe_slice_level_set5_0 Reset: hex:0x000; |
| [08:00] RW/V |
cdr_ffe_slice_level_set5_p1 Reset: hex:0x0a8; |
+0x00000914 Register(32 bit) cdr_ffe_slicer_level_set6_control
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e914 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x560000a8 | |
| Unaffected | 0x80200e00 | ||
| Undefined | 0x80200e00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_slice_level_set6_m1 | - | cdr_ffe_slice_level_set6_0 | - | cdr_ffe_slice_level_set6_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [30:22] RW/V |
cdr_ffe_slice_level_set6_m1 Reset: hex:0x158; |
| [20:12] RW/V |
cdr_ffe_slice_level_set6_0 Reset: hex:0x000; |
| [08:00] RW/V |
cdr_ffe_slice_level_set6_p1 Reset: hex:0x0a8; |
+0x00000918 Register(32 bit) cdr_ffe_slicer_level_set7_control
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e918 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x560000a8 | |
| Unaffected | 0x80200e00 | ||
| Undefined | 0x80200e00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_slice_level_set7_m1 | - | cdr_ffe_slice_level_set7_0 | - | cdr_ffe_slice_level_set7_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [30:22] RW/V |
cdr_ffe_slice_level_set7_m1 Reset: hex:0x158; |
| [20:12] RW/V |
cdr_ffe_slice_level_set7_0 Reset: hex:0x000; |
| [08:00] RW/V |
cdr_ffe_slice_level_set7_p1 Reset: hex:0x0a8; |
+0x0000091c Register(32 bit) cdr_ffe_slicer_level_set8_control
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e91c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x560000a8 | |
| Unaffected | 0x80200e00 | ||
| Undefined | 0x80200e00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_slice_level_set8_m1 | - | cdr_ffe_slice_level_set8_0 | - | cdr_ffe_slice_level_set8_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [30:22] RW/V |
cdr_ffe_slice_level_set8_m1 Reset: hex:0x158; |
| [20:12] RW/V |
cdr_ffe_slice_level_set8_0 Reset: hex:0x000; |
| [08:00] RW/V |
cdr_ffe_slice_level_set8_p1 Reset: hex:0x0a8; |
+0x00000920 Register(32 bit) cdr_ffe_slicer_level_set9_control
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e920 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x560000a8 | |
| Unaffected | 0x80200e00 | ||
| Undefined | 0x80200e00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_slice_level_set9_m1 | - | cdr_ffe_slice_level_set9_0 | - | cdr_ffe_slice_level_set9_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [30:22] RW/V |
cdr_ffe_slice_level_set9_m1 Reset: hex:0x158; |
| [20:12] RW/V |
cdr_ffe_slice_level_set9_0 Reset: hex:0x000; |
| [08:00] RW/V |
cdr_ffe_slice_level_set9_p1 Reset: hex:0x0a8; |
+0x00000924 Register(32 bit) cdr_ffe_slicer_level_set10_control
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e924 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x560000a8 | |
| Unaffected | 0x80200e00 | ||
| Undefined | 0x80200e00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_slice_level_set10_m1 | - | cdr_ffe_slice_level_set10_0 | - | cdr_ffe_slice_level_set10_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [30:22] RW/V |
cdr_ffe_slice_level_set10_m1 Reset: hex:0x158; |
| [20:12] RW/V |
cdr_ffe_slice_level_set10_0 Reset: hex:0x000; |
| [08:00] RW/V |
cdr_ffe_slice_level_set10_p1 Reset: hex:0x0a8; |
+0x00000928 Register(32 bit) cdr_ffe_slicer_level_set11_control
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e928 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x560000a8 | |
| Unaffected | 0x80200e00 | ||
| Undefined | 0x80200e00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_slice_level_set11_m1 | - | cdr_ffe_slice_level_set11_0 | - | cdr_ffe_slice_level_set11_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [30:22] RW/V |
cdr_ffe_slice_level_set11_m1 Reset: hex:0x158; |
| [20:12] RW/V |
cdr_ffe_slice_level_set11_0 Reset: hex:0x000; |
| [08:00] RW/V |
cdr_ffe_slice_level_set11_p1 Reset: hex:0x0a8; |
+0x0000092c Register(32 bit) cdr_ffe_slicer_level_set12_control
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e92c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x560000a8 | |
| Unaffected | 0x80200e00 | ||
| Undefined | 0x80200e00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_slice_level_set12_m1 | - | cdr_ffe_slice_level_set12_0 | - | cdr_ffe_slice_level_set12_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [30:22] RW/V |
cdr_ffe_slice_level_set12_m1 Reset: hex:0x158; |
| [20:12] RW/V |
cdr_ffe_slice_level_set12_0 Reset: hex:0x000; |
| [08:00] RW/V |
cdr_ffe_slice_level_set12_p1 Reset: hex:0x0a8; |
+0x00000930 Register(32 bit) cdr_ffe_slicer_level_set13_control
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e930 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x560000a8 | |
| Unaffected | 0x80200e00 | ||
| Undefined | 0x80200e00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_slice_level_set13_m1 | - | cdr_ffe_slice_level_set13_0 | - | cdr_ffe_slice_level_set13_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [30:22] RW/V |
cdr_ffe_slice_level_set13_m1 Reset: hex:0x158; |
| [20:12] RW/V |
cdr_ffe_slice_level_set13_0 Reset: hex:0x000; |
| [08:00] RW/V |
cdr_ffe_slice_level_set13_p1 Reset: hex:0x0a8; |
+0x00000934 Register(32 bit) cdr_ffe_slicer_level_set14_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e934 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x560000a8 | |
| Unaffected | 0x80200e00 | ||
| Undefined | 0x80200e00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_slice_level_set14_m1 | - | cdr_ffe_slice_level_set14_0 | - | cdr_ffe_slice_level_set14_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [30:22] RW/V |
cdr_ffe_slice_level_set14_m1 Reset: hex:0x158; |
| [20:12] RW/V |
cdr_ffe_slice_level_set14_0 Reset: hex:0x000; |
| [08:00] RW/V |
cdr_ffe_slice_level_set14_p1 Reset: hex:0x0a8; |
+0x00000938 Register(32 bit) cdr_ffe_slicer_level_set15_control
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e938 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x560000a8 | |
| Unaffected | 0x80200e00 | ||
| Undefined | 0x80200e00 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_slice_level_set15_m1 | - | cdr_ffe_slice_level_set15_0 | - | cdr_ffe_slice_level_set15_p1 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [30:22] RW/V |
cdr_ffe_slice_level_set15_m1 Reset: hex:0x158; |
| [20:12] RW/V |
cdr_ffe_slice_level_set15_0 Reset: hex:0x000; |
| [08:00] RW/V |
cdr_ffe_slice_level_set15_p1 Reset: hex:0x0a8; |
+0x00000940 Register(32 bit) cdr_ffe_err_level_m1m3_set0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e940 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000209a8 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set0_m3 | cdr_ffe_err_level_set0_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set0_m3 Reset: hex:0x104; |
| [08:00] RW/V |
cdr_ffe_err_level_set0_m1 Reset: hex:0x1a8; |
+0x00000944 Register(32 bit) cdr_ffe_err_level_p1p3_set0
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e944 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0001f058 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set0_p3 | cdr_ffe_err_level_set0_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set0_p3 Reset: hex:0x0f8; |
| [08:00] RW/V |
cdr_ffe_err_level_set0_p1 Reset: hex:0x058; |
+0x00000948 Register(32 bit) cdr_ffe_err_level_m1m3_set1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e948 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000209a8 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set1_m3 | cdr_ffe_err_level_set1_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set1_m3 Reset: hex:0x104; |
| [08:00] RW/V |
cdr_ffe_err_level_set1_m1 Reset: hex:0x1a8; |
+0x0000094c Register(32 bit) cdr_ffe_err_level_p1p3_set1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e94c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0001f058 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set1_p3 | cdr_ffe_err_level_set1_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set1_p3 Reset: hex:0x0f8; |
| [08:00] RW/V |
cdr_ffe_err_level_set1_p1 Reset: hex:0x058; |
+0x00000950 Register(32 bit) cdr_ffe_err_level_m1m3_set2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e950 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000209a8 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set2_m3 | cdr_ffe_err_level_set2_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set2_m3 Reset: hex:0x104; |
| [08:00] RW/V |
cdr_ffe_err_level_set2_m1 Reset: hex:0x1a8; |
+0x00000954 Register(32 bit) cdr_ffe_err_level_p1p3_set2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e954 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0001f058 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set2_p3 | cdr_ffe_err_level_set2_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set2_p3 Reset: hex:0x0f8; |
| [08:00] RW/V |
cdr_ffe_err_level_set2_p1 Reset: hex:0x058; |
+0x00000958 Register(32 bit) cdr_ffe_err_level_m1m3_set3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e958 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000209a8 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set3_m3 | cdr_ffe_err_level_set3_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set3_m3 Reset: hex:0x104; |
| [08:00] RW/V |
cdr_ffe_err_level_set3_m1 Reset: hex:0x1a8; |
+0x0000095c Register(32 bit) cdr_ffe_err_level_p1p3_set3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e95c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0001f058 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set3_p3 | cdr_ffe_err_level_set3_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set3_p3 Reset: hex:0x0f8; |
| [08:00] RW/V |
cdr_ffe_err_level_set3_p1 Reset: hex:0x058; |
+0x00000960 Register(32 bit) cdr_ffe_err_level_m1m3_set4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e960 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000209a8 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set4_m3 | cdr_ffe_err_level_set4_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set4_m3 Reset: hex:0x104; |
| [08:00] RW/V |
cdr_ffe_err_level_set4_m1 Reset: hex:0x1a8; |
+0x00000964 Register(32 bit) cdr_ffe_err_level_p1p3_set4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e964 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0001f058 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set4_p3 | cdr_ffe_err_level_set4_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set4_p3 Reset: hex:0x0f8; |
| [08:00] RW/V |
cdr_ffe_err_level_set4_p1 Reset: hex:0x058; |
+0x00000968 Register(32 bit) cdr_ffe_err_level_m1m3_set5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e968 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000209a8 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set5_m3 | cdr_ffe_err_level_set5_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set5_m3 Reset: hex:0x104; |
| [08:00] RW/V |
cdr_ffe_err_level_set5_m1 Reset: hex:0x1a8; |
+0x0000096c Register(32 bit) cdr_ffe_err_level_p1p3_set5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e96c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0001f058 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set5_p3 | cdr_ffe_err_level_set5_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set5_p3 Reset: hex:0x0f8; |
| [08:00] RW/V |
cdr_ffe_err_level_set5_p1 Reset: hex:0x058; |
+0x00000970 Register(32 bit) cdr_ffe_err_level_m1m3_set6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e970 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000209a8 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set6_m3 | cdr_ffe_err_level_set6_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set6_m3 Reset: hex:0x104; |
| [08:00] RW/V |
cdr_ffe_err_level_set6_m1 Reset: hex:0x1a8; |
+0x00000974 Register(32 bit) cdr_ffe_err_level_p1p3_set6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e974 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0001f058 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set6_p3 | cdr_ffe_err_level_set6_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set6_p3 Reset: hex:0x0f8; |
| [08:00] RW/V |
cdr_ffe_err_level_set6_p1 Reset: hex:0x058; |
+0x00000978 Register(32 bit) cdr_ffe_err_level_m1m3_set7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e978 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000209a8 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set7_m3 | cdr_ffe_err_level_set7_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set7_m3 Reset: hex:0x104; |
| [08:00] RW/V |
cdr_ffe_err_level_set7_m1 Reset: hex:0x1a8; |
+0x0000097c Register(32 bit) cdr_ffe_err_level_p1p3_set7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e97c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0001f058 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set7_p3 | cdr_ffe_err_level_set7_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set7_p3 Reset: hex:0x0f8; |
| [08:00] RW/V |
cdr_ffe_err_level_set7_p1 Reset: hex:0x058; |
+0x00000980 Register(32 bit) cdr_ffe_err_level_m1m3_set8
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e980 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000209a8 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set8_m3 | cdr_ffe_err_level_set8_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set8_m3 Reset: hex:0x104; |
| [08:00] RW/V |
cdr_ffe_err_level_set8_m1 Reset: hex:0x1a8; |
+0x00000984 Register(32 bit) cdr_ffe_err_level_p1p3_set8
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e984 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0001f058 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set8_p3 | cdr_ffe_err_level_set8_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set8_p3 Reset: hex:0x0f8; |
| [08:00] RW/V |
cdr_ffe_err_level_set8_p1 Reset: hex:0x058; |
+0x00000988 Register(32 bit) cdr_ffe_err_level_m1m3_set9
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e988 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000209a8 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set9_m3 | cdr_ffe_err_level_set9_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set9_m3 Reset: hex:0x104; |
| [08:00] RW/V |
cdr_ffe_err_level_set9_m1 Reset: hex:0x1a8; |
+0x0000098c Register(32 bit) cdr_ffe_err_level_p1p3_set9
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e98c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0001f058 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set9_p3 | cdr_ffe_err_level_set9_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set9_p3 Reset: hex:0x0f8; |
| [08:00] RW/V |
cdr_ffe_err_level_set9_p1 Reset: hex:0x058; |
+0x00000990 Register(32 bit) cdr_ffe_err_level_m1m3_set10
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e990 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000209a8 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set10_m3 | cdr_ffe_err_level_set10_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set10_m3 Reset: hex:0x104; |
| [08:00] RW/V |
cdr_ffe_err_level_set10_m1 Reset: hex:0x1a8; |
+0x00000994 Register(32 bit) cdr_ffe_err_level_p1p3_set10
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e994 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0001f058 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set10_p3 | cdr_ffe_err_level_set10_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set10_p3 Reset: hex:0x0f8; |
| [08:00] RW/V |
cdr_ffe_err_level_set10_p1 Reset: hex:0x058; |
+0x00000998 Register(32 bit) cdr_ffe_err_level_m1m3_set11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e998 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000209a8 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set11_m3 | cdr_ffe_err_level_set11_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set11_m3 Reset: hex:0x104; |
| [08:00] RW/V |
cdr_ffe_err_level_set11_m1 Reset: hex:0x1a8; |
+0x0000099c Register(32 bit) cdr_ffe_err_level_p1p3_set11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e99c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0001f058 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set11_p3 | cdr_ffe_err_level_set11_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set11_p3 Reset: hex:0x0f8; |
| [08:00] RW/V |
cdr_ffe_err_level_set11_p1 Reset: hex:0x058; |
+0x000009a0 Register(32 bit) cdr_ffe_err_level_m1m3_set12
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9a0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000209a8 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set12_m3 | cdr_ffe_err_level_set12_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set12_m3 Reset: hex:0x104; |
| [08:00] RW/V |
cdr_ffe_err_level_set12_m1 Reset: hex:0x1a8; |
+0x000009a4 Register(32 bit) cdr_ffe_err_level_p1p3_set12
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9a4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0001f058 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set12_p3 | cdr_ffe_err_level_set12_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set12_p3 Reset: hex:0x0f8; |
| [08:00] RW/V |
cdr_ffe_err_level_set12_p1 Reset: hex:0x058; |
+0x000009a8 Register(32 bit) cdr_ffe_err_level_m1m3_set13
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9a8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000209a8 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set13_m3 | cdr_ffe_err_level_set13_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set13_m3 Reset: hex:0x104; |
| [08:00] RW/V |
cdr_ffe_err_level_set13_m1 Reset: hex:0x1a8; |
+0x000009ac Register(32 bit) cdr_ffe_err_level_p1p3_set13
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9ac at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0001f058 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set13_p3 | cdr_ffe_err_level_set13_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set13_p3 Reset: hex:0x0f8; |
| [08:00] RW/V |
cdr_ffe_err_level_set13_p1 Reset: hex:0x058; |
+0x000009b0 Register(32 bit) cdr_ffe_err_level_m1m3_set14
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9b0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000209a8 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set14_m3 | cdr_ffe_err_level_set14_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set14_m3 Reset: hex:0x104; |
| [08:00] RW/V |
cdr_ffe_err_level_set14_m1 Reset: hex:0x1a8; |
+0x000009b4 Register(32 bit) cdr_ffe_err_level_p1p3_set14
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9b4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0001f058 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set14_p3 | cdr_ffe_err_level_set14_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set14_p3 Reset: hex:0x0f8; |
| [08:00] RW/V |
cdr_ffe_err_level_set14_p1 Reset: hex:0x058; |
+0x000009b8 Register(32 bit) cdr_ffe_err_level_m1m3_set15
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9b8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000209a8 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set15_m3 | cdr_ffe_err_level_set15_m1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set15_m3 Reset: hex:0x104; |
| [08:00] RW/V |
cdr_ffe_err_level_set15_m1 Reset: hex:0x1a8; |
+0x000009c0 Register(32 bit) cdr_ffe_err_level_p1p3_set15
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9c0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0001f058 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_err_level_set15_p3 | cdr_ffe_err_level_set15_p1 | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [17:09] RW/V |
cdr_ffe_err_level_set15_p3 Reset: hex:0x0f8; |
| [08:00] RW/V |
cdr_ffe_err_level_set15_p1 Reset: hex:0x058; |
+0x000009c8 Register(32 bit) cdr_ffe_post1_set0to3
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9c8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post1_coeff_set3 | cdr_ffe_post1_coeff_set2 | cdr_ffe_post1_coeff_set1 | cdr_ffe_post1_coeff_set0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post1_coeff_set3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post1_coeff_set2 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post1_coeff_set1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post1_coeff_set0 Reset: hex:0x00; |
+0x000009cc Register(32 bit) cdr_ffe_post1_set4to7
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9cc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post1_coeff_set7 | cdr_ffe_post1_coeff_set6 | cdr_ffe_post1_coeff_set5 | cdr_ffe_post1_coeff_set4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post1_coeff_set7 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post1_coeff_set6 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post1_coeff_set5 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post1_coeff_set4 Reset: hex:0x00; |
+0x000009d0 Register(32 bit) cdr_ffe_post1_set8to11
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9d0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post1_coeff_set11 | cdr_ffe_post1_coeff_set10 | cdr_ffe_post1_coeff_set9 | cdr_ffe_post1_coeff_set8 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post1_coeff_set11 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post1_coeff_set10 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post1_coeff_set9 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post1_coeff_set8 Reset: hex:0x00; |
+0x000009d4 Register(32 bit) cdr_ffe_post1_set12to15
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9d4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post1_coeff_set15 | cdr_ffe_post1_coeff_set14 | cdr_ffe_post1_coeff_set13 | cdr_ffe_post1_coeff_set12 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post1_coeff_set15 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post1_coeff_set14 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post1_coeff_set13 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post1_coeff_set12 Reset: hex:0x00; |
+0x000009d8 Register(32 bit) cdr_ffe_control_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9d8 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x04080000 | |
| Unaffected | 0x80000802 | ||
| Undefined | 0x80000802 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 |
| Name | - | cdr_ffe_updn_inv_cb | cdr_ffe_timer_max | cdr_ffe_stats_max | - | cdr_ffe_hold_en | cdr_ffe_post1_up_dis | cdr_ffe_pre1_up_dis | - | cdr_ffe_7tap_mode | ||||||||||||||||||||||
| Access | - | RW | RW | RW | - | RW | RW | RW | - | RW | ||||||||||||||||||||||
| [30:30] RW |
cdr_ffe_updn_inv_cb Reset: hex:0x0; |
| [29:22] RW |
cdr_ffe_timer_max Reset: hex:0x10; |
| [21:12] RW |
cdr_ffe_stats_max Reset: hex:0x080; |
| [10:04] RW |
cdr_ffe_hold_en Reset: hex:0x00; |
| [03:03] RW |
cdr_ffe_post1_up_dis Reset: hex:0x0; |
| [02:02] RW |
cdr_ffe_pre1_up_dis Reset: hex:0x0; |
| [00:00] RW |
cdr_ffe_7tap_mode Reset: hex:0x0; |
+0x000009dc Register(32 bit) cdr_ffe_control_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9dc at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00010410 | |
| Unaffected | 0xfffe0000 | ||
| Undefined | 0xfffe0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_coarse_mu_en | cdr_ffe_mu_fine | cdr_ffe_mu_coarse | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [16:16] RW |
cdr_ffe_coarse_mu_en Reset: hex:0x1; |
| [15:08] RW |
cdr_ffe_mu_fine Reset: hex:0x04; |
| [07:00] RW |
cdr_ffe_mu_coarse Reset: hex:0x10; |
+0x000009e0 Register(32 bit) cdr_ffe_control_2
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9e0 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0000201f | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 1 | 1 | 1 | 1 | 1 |
| Name | - | cdr_ffe_init_val_w0 | - | cdr_ffe_tap_min_w0 | - | cdr_ffe_tap_max_w0 | ||||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | ||||||||||||||||||||||||||
| [21:16] RW |
cdr_ffe_init_val_w0 Reset: hex:0x00; |
| [13:08] RW |
cdr_ffe_tap_min_w0 Reset: hex:0x20; |
| [05:00] RW |
cdr_ffe_tap_max_w0 Reset: hex:0x1f; |
+0x000009e4 Register(32 bit) lms_avg_updn_status_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9e4 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_ofc_avg_updn | adcofc_avg_updn | ofc_avg_updn | cdr_ffe_vref_avg_updn | edgvref_avg_updn | cdr_ffe_avg_updn | ||||||||||||||||||||||||||
| Access | RO/V | RO/V | RO/V | RO/V | RO/V | RO/V | ||||||||||||||||||||||||||
| [31:26] RO/V |
cdr_ffe_ofc_avg_updn Reset: hex:0x00; |
| [25:20] RO/V |
adcofc_avg_updn Reset: hex:0x00; |
| [19:14] RO/V |
ofc_avg_updn Reset: hex:0x00; |
| [13:10] RO/V |
cdr_ffe_vref_avg_updn Reset: hex:0x0; |
| [09:07] RO/V |
edgvref_avg_updn Reset: hex:0x0; |
| [06:00] RO/V |
cdr_ffe_avg_updn Reset: hex:0x00; |
+0x000009e8 Register(32 bit) cdr_ffe_vref_control_1
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9e8 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000040 | |
| Unaffected | 0xfffff800 | ||
| Undefined | 0xfffff800 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_vref_int_iter_max | cdr_ffe_vref_int_iter_bypass | cdr_ffe_vref_hold_en | cdr_ffe_vref_pos_updn_inv_cb | cdr_ffe_vref_neg_updn_inv_cb | ||||||||||||||||||||||||||
| Access | - | RW | RW | RW | RW | RW | ||||||||||||||||||||||||||
| [10:07] RW |
cdr_ffe_vref_int_iter_max Reset: hex:0x0; |
| [06:06] RW |
cdr_ffe_vref_int_iter_bypass Reset: hex:0x1; |
| [05:02] RW |
cdr_ffe_vref_hold_en Reset: hex:0x0; |
| [01:01] RW |
cdr_ffe_vref_pos_updn_inv_cb Reset: hex:0x0; |
| [00:00] RW |
cdr_ffe_vref_neg_updn_inv_cb Reset: hex:0x0; |
+0x000009ec Register(32 bit) cdr_ffe_vref_control_2
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9ec at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00036120 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_vref_init_val_1 | cdr_ffe_vref_init_val_0 | |||||||||||||||||||||||||||||
| Access | - | RW | RW | |||||||||||||||||||||||||||||
| [17:09] RW |
cdr_ffe_vref_init_val_1 Reset: hex:0x1b0; |
| [08:00] RW |
cdr_ffe_vref_init_val_0 Reset: hex:0x120; |
+0x000009f0 Register(32 bit) cdr_ffe_vref_control_3
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9f0 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0001c050 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_vref_init_val_3 | cdr_ffe_vref_init_val_2 | |||||||||||||||||||||||||||||
| Access | - | RW | RW | |||||||||||||||||||||||||||||
| [17:09] RW |
cdr_ffe_vref_init_val_3 Reset: hex:0x0e0; |
| [08:00] RW |
cdr_ffe_vref_init_val_2 Reset: hex:0x050; |
+0x000009f4 Register(32 bit) cdr_ffe_vref_control_4
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9f4 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00004008 | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_vref_stats_max | cdr_ffe_vref_timer_max | |||||||||||||||||||||||||||||
| Access | - | RW | RW | |||||||||||||||||||||||||||||
| [17:08] RW |
cdr_ffe_vref_stats_max Reset: hex:0x040; |
| [07:00] RW |
cdr_ffe_vref_timer_max Reset: hex:0x08; |
+0x000009f8 Register(32 bit) cdr_ffe_vref_control_5
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9f8 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000200ff | |
| Unaffected | 0xfffc0000 | ||
| Undefined | 0xfffc0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Name | - | cdr_ffe_vref_tap_min | cdr_ffe_vref_tap_max | |||||||||||||||||||||||||||||
| Access | - | RW | RW | |||||||||||||||||||||||||||||
| [17:09] RW |
cdr_ffe_vref_tap_min Reset: hex:0x100; |
| [08:00] RW |
cdr_ffe_vref_tap_max Reset: hex:0x0ff; |
+0x000009fc Register(32 bit) cdr_ffe_vref_control_6
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782e9fc at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00001021 | |
| Unaffected | 0xffec0200 | ||
| Undefined | 0xffec0200 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | - | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
| Name | - | cdr_ffe_vref_thrs_sel | - | cdr_ffe_vref_mu_fine | - | cdr_ffe_vref_mu_coarse | cdr_ffe_vref_coarse_mu_en | |||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | RW | |||||||||||||||||||||||||
| [20:20] RW |
cdr_ffe_vref_thrs_sel Reset: hex:0x0; |
| [17:10] RW |
cdr_ffe_vref_mu_fine Reset: hex:0x04; |
| [08:01] RW |
cdr_ffe_vref_mu_coarse Reset: hex:0x10; |
| [00:00] RW |
cdr_ffe_vref_coarse_mu_en Reset: hex:0x1; |
+0x00000a04 Register(32 bit) cdr_ffe_ofc_control_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea04 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00010020 | |
| Unaffected | 0xf0380000 | ||
| Undefined | 0xf0380000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | - | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_ofc_hold_en | - | cdr_ffe_ofc_stats_max | cdr_ffe_ofc_timer_max | cdr_ffe_ofc_updn_inv_cb | ||||||||||||||||||||||||||
| Access | - | RW | - | RW | RW | RW | ||||||||||||||||||||||||||
| [27:22] RW |
cdr_ffe_ofc_hold_en Reset: hex:0x00; |
| [18:09] RW |
cdr_ffe_ofc_stats_max Reset: hex:0x080; |
| [08:01] RW |
cdr_ffe_ofc_timer_max Reset: hex:0x10; |
| [00:00] RW |
cdr_ffe_ofc_updn_inv_cb Reset: hex:0x0; |
+0x00000a08 Register(32 bit) cdr_ffe_ofc_control_1a
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea08 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0005a168 | |
| Unaffected | 0xe0080200 | ||
| Undefined | 0xe0080200 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | - | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_ofc_init_val_2 | - | cdr_ffe_ofc_init_val_1 | - | cdr_ffe_ofc_init_val_0 | ||||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | ||||||||||||||||||||||||||
| [28:20] RW |
cdr_ffe_ofc_init_val_2 Reset: hex:0x000; |
| [18:10] RW |
cdr_ffe_ofc_init_val_1 Reset: hex:0x168; |
| [08:00] RW |
cdr_ffe_ofc_init_val_0 Reset: hex:0x168; |
+0x00000a0c Register(32 bit) cdr_ffe_ofc_control_1b
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea0c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x09826000 | |
| Unaffected | 0xe0080200 | ||
| Undefined | 0xe0080200 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_ofc_init_val_5 | - | cdr_ffe_ofc_init_val_4 | - | cdr_ffe_ofc_init_val_3 | ||||||||||||||||||||||||||
| Access | - | RW | - | RW | - | RW | ||||||||||||||||||||||||||
| [28:20] RW |
cdr_ffe_ofc_init_val_5 Reset: hex:0x098; |
| [18:10] RW |
cdr_ffe_ofc_init_val_4 Reset: hex:0x098; |
| [08:00] RW |
cdr_ffe_ofc_init_val_3 Reset: hex:0x000; |
+0x00000a10 Register(32 bit) cdr_ffe_ofc_control_2
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea10 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00010410 | |
| Unaffected | 0xfffe0000 | ||
| Undefined | 0xfffe0000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_ofc_coarse_mu_en | cdr_ffe_ofc_mu_fine | cdr_ffe_ofc_mu_coarse | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [16:16] RW |
cdr_ffe_ofc_coarse_mu_en Reset: hex:0x1; |
| [15:08] RW |
cdr_ffe_ofc_mu_fine Reset: hex:0x04; |
| [07:00] RW |
cdr_ffe_ofc_mu_coarse Reset: hex:0x10; |
+0x00000a14 Register(32 bit) cdr_ffe_ofc_control_3
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea14 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000400ff | |
| Unaffected | 0xfff80200 | ||
| Undefined | 0xfff80200 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Name | - | cdr_ffe_ofc_tap_min | - | cdr_ffe_ofc_tap_max | ||||||||||||||||||||||||||||
| Access | - | RW | - | RW | ||||||||||||||||||||||||||||
| [18:10] RW |
cdr_ffe_ofc_tap_min Reset: hex:0x100; |
| [08:00] RW |
cdr_ffe_ofc_tap_max Reset: hex:0x0ff; |
+0x00000a18 Register(32 bit) cdr_ffe_ofc_status_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea18 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xe0080200 | ||
| Undefined | 0xe0080200 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_ofc_tap_zr | - | cdr_ffe_ofc_tap_lo | - | cdr_ffe_ofc_tap_hi | ||||||||||||||||||||||||||
| Access | - | RO/V | - | RO/V | - | RO/V | ||||||||||||||||||||||||||
| [28:20] RO/V |
cdr_ffe_ofc_tap_zr Reset: hex:0x000; |
| [18:10] RO/V |
cdr_ffe_ofc_tap_lo Reset: hex:0x000; |
| [08:00] RO/V |
cdr_ffe_ofc_tap_hi Reset: hex:0x000; |
+0x00000a1c Register(32 bit) cdr_ffe_pre1_set0to3_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea1c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_pre1_coeff_set3_frac | cdr_ffe_pre1_coeff_set2_frac | cdr_ffe_pre1_coeff_set1_frac | cdr_ffe_pre1_coeff_set0_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_pre1_coeff_set3_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_pre1_coeff_set2_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_pre1_coeff_set1_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_pre1_coeff_set0_frac Reset: hex:0x00; |
+0x00000a20 Register(32 bit) cdr_ffe_pre1_set4to7_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea20 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_pre1_coeff_set7_frac | cdr_ffe_pre1_coeff_set6_frac | cdr_ffe_pre1_coeff_set5_frac | cdr_ffe_pre1_coeff_set4_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_pre1_coeff_set7_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_pre1_coeff_set6_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_pre1_coeff_set5_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_pre1_coeff_set4_frac Reset: hex:0x00; |
+0x00000a24 Register(32 bit) cdr_ffe_pre1_set8to11_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea24 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_pre1_coeff_set11_frac | cdr_ffe_pre1_coeff_set10_frac | cdr_ffe_pre1_coeff_set9_frac | cdr_ffe_pre1_coeff_set8_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_pre1_coeff_set11_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_pre1_coeff_set10_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_pre1_coeff_set9_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_pre1_coeff_set8_frac Reset: hex:0x00; |
+0x00000a28 Register(32 bit) cdr_ffe_pre1_set12to15_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea28 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_pre1_coeff_set15_frac | cdr_ffe_pre1_coeff_set14_frac | cdr_ffe_pre1_coeff_set13_frac | cdr_ffe_pre1_coeff_set12_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_pre1_coeff_set15_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_pre1_coeff_set14_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_pre1_coeff_set13_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_pre1_coeff_set12_frac Reset: hex:0x00; |
+0x00000a2c Register(32 bit) cdr_ffe_post1_set0to3_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea2c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post1_coeff_set3_frac | cdr_ffe_post1_coeff_set2_frac | cdr_ffe_post1_coeff_set1_frac | cdr_ffe_post1_coeff_set0_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post1_coeff_set3_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post1_coeff_set2_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post1_coeff_set1_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post1_coeff_set0_frac Reset: hex:0x00; |
+0x00000a30 Register(32 bit) cdr_ffe_post1_set4to7_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea30 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post1_coeff_set7_frac | cdr_ffe_post1_coeff_set6_frac | cdr_ffe_post1_coeff_set5_frac | cdr_ffe_post1_coeff_set4_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post1_coeff_set7_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post1_coeff_set6_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post1_coeff_set5_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post1_coeff_set4_frac Reset: hex:0x00; |
+0x00000a34 Register(32 bit) cdr_ffe_post1_set8to11_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea34 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post1_coeff_set11_frac | cdr_ffe_post1_coeff_set10_frac | cdr_ffe_post1_coeff_set9_frac | cdr_ffe_post1_coeff_set8_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post1_coeff_set11_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post1_coeff_set10_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post1_coeff_set9_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post1_coeff_set8_frac Reset: hex:0x00; |
+0x00000a38 Register(32 bit) cdr_ffe_post1_set12to15_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea38 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post1_coeff_set15_frac | cdr_ffe_post1_coeff_set14_frac | cdr_ffe_post1_coeff_set13_frac | cdr_ffe_post1_coeff_set12_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post1_coeff_set15_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post1_coeff_set14_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post1_coeff_set13_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post1_coeff_set12_frac Reset: hex:0x00; |
+0x00000a3c Register(32 bit) cdr_ffe_err_level_frac_set0_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea3c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_err_level_frac_set0_p3 | cdr_ffe_err_level_frac_set0_p1 | cdr_ffe_err_level_frac_set0_m1 | cdr_ffe_err_level_frac_set0_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_err_level_frac_set0_p3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_err_level_frac_set0_p1 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_err_level_frac_set0_m1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_err_level_frac_set0_m3 Reset: hex:0x00; |
+0x00000a40 Register(32 bit) cdr_ffe_err_level_frac_set1_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea40 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_err_level_frac_set1_p3 | cdr_ffe_err_level_frac_set1_p1 | cdr_ffe_err_level_frac_set1_m1 | cdr_ffe_err_level_frac_set1_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_err_level_frac_set1_p3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_err_level_frac_set1_p1 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_err_level_frac_set1_m1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_err_level_frac_set1_m3 Reset: hex:0x00; |
+0x00000a44 Register(32 bit) cdr_ffe_err_level_frac_set2_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea44 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_err_level_frac_set2_p3 | cdr_ffe_err_level_frac_set2_p1 | cdr_ffe_err_level_frac_set2_m1 | cdr_ffe_err_level_frac_set2_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_err_level_frac_set2_p3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_err_level_frac_set2_p1 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_err_level_frac_set2_m1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_err_level_frac_set2_m3 Reset: hex:0x00; |
+0x00000a48 Register(32 bit) cdr_ffe_err_level_frac_set3_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea48 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_err_level_frac_set3_p3 | cdr_ffe_err_level_frac_set3_p1 | cdr_ffe_err_level_frac_set3_m1 | cdr_ffe_err_level_frac_set3_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_err_level_frac_set3_p3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_err_level_frac_set3_p1 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_err_level_frac_set3_m1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_err_level_frac_set3_m3 Reset: hex:0x00; |
+0x00000a4c Register(32 bit) cdr_ffe_err_level_frac_set4_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea4c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_err_level_frac_set4_p3 | cdr_ffe_err_level_frac_set4_p1 | cdr_ffe_err_level_frac_set4_m1 | cdr_ffe_err_level_frac_set4_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_err_level_frac_set4_p3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_err_level_frac_set4_p1 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_err_level_frac_set4_m1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_err_level_frac_set4_m3 Reset: hex:0x00; |
+0x00000a50 Register(32 bit) cdr_ffe_err_level_frac_set5_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea50 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_err_level_frac_set5_p3 | cdr_ffe_err_level_frac_set5_p1 | cdr_ffe_err_level_frac_set5_m1 | cdr_ffe_err_level_frac_set5_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_err_level_frac_set5_p3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_err_level_frac_set5_p1 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_err_level_frac_set5_m1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_err_level_frac_set5_m3 Reset: hex:0x00; |
+0x00000a54 Register(32 bit) cdr_ffe_err_level_frac_set6_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea54 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_err_level_frac_set6_p3 | cdr_ffe_err_level_frac_set6_p1 | cdr_ffe_err_level_frac_set6_m1 | cdr_ffe_err_level_frac_set6_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_err_level_frac_set6_p3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_err_level_frac_set6_p1 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_err_level_frac_set6_m1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_err_level_frac_set6_m3 Reset: hex:0x00; |
+0x00000a58 Register(32 bit) cdr_ffe_err_level_frac_set7_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea58 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_err_level_frac_set7_p3 | cdr_ffe_err_level_frac_set7_p1 | cdr_ffe_err_level_frac_set7_m1 | cdr_ffe_err_level_frac_set7_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_err_level_frac_set7_p3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_err_level_frac_set7_p1 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_err_level_frac_set7_m1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_err_level_frac_set7_m3 Reset: hex:0x00; |
+0x00000a5c Register(32 bit) cdr_ffe_err_level_frac_set8_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea5c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_err_level_frac_set8_p3 | cdr_ffe_err_level_frac_set8_p1 | cdr_ffe_err_level_frac_set8_m1 | cdr_ffe_err_level_frac_set8_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_err_level_frac_set8_p3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_err_level_frac_set8_p1 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_err_level_frac_set8_m1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_err_level_frac_set8_m3 Reset: hex:0x00; |
+0x00000a60 Register(32 bit) cdr_ffe_err_level_frac_set9_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea60 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_err_level_frac_set9_p3 | cdr_ffe_err_level_frac_set9_p1 | cdr_ffe_err_level_frac_set9_m1 | cdr_ffe_err_level_frac_set9_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_err_level_frac_set9_p3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_err_level_frac_set9_p1 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_err_level_frac_set9_m1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_err_level_frac_set9_m3 Reset: hex:0x00; |
+0x00000a64 Register(32 bit) cdr_ffe_err_level_frac_set10_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea64 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_err_level_frac_set10_p3 | cdr_ffe_err_level_frac_set10_p1 | cdr_ffe_err_level_frac_set10_m1 | cdr_ffe_err_level_frac_set10_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_err_level_frac_set10_p3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_err_level_frac_set10_p1 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_err_level_frac_set10_m1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_err_level_frac_set10_m3 Reset: hex:0x00; |
+0x00000a68 Register(32 bit) cdr_ffe_err_level_frac_set11_0
placeholder
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea68 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_err_level_frac_set11_p3 | cdr_ffe_err_level_frac_set11_p1 | cdr_ffe_err_level_frac_set11_m1 | cdr_ffe_err_level_frac_set11_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_err_level_frac_set11_p3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_err_level_frac_set11_p1 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_err_level_frac_set11_m1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_err_level_frac_set11_m3 Reset: hex:0x00; |
+0x00000a6c Register(32 bit) cdr_ffe_err_level_frac_set12_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea6c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_err_level_frac_set12_p3 | cdr_ffe_err_level_frac_set12_p1 | cdr_ffe_err_level_frac_set12_m1 | cdr_ffe_err_level_frac_set12_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_err_level_frac_set12_p3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_err_level_frac_set12_p1 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_err_level_frac_set12_m1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_err_level_frac_set12_m3 Reset: hex:0x00; |
+0x00000a70 Register(32 bit) cdr_ffe_err_level_frac_set13_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea70 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_err_level_frac_set13_p3 | cdr_ffe_err_level_frac_set13_p1 | cdr_ffe_err_level_frac_set13_m1 | cdr_ffe_err_level_frac_set13_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_err_level_frac_set13_p3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_err_level_frac_set13_p1 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_err_level_frac_set13_m1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_err_level_frac_set13_m3 Reset: hex:0x00; |
+0x00000a74 Register(32 bit) cdr_ffe_err_level_frac_set14_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea74 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_err_level_frac_set14_p3 | cdr_ffe_err_level_frac_set14_p1 | cdr_ffe_err_level_frac_set14_m1 | cdr_ffe_err_level_frac_set14_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_err_level_frac_set14_p3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_err_level_frac_set14_p1 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_err_level_frac_set14_m1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_err_level_frac_set14_m3 Reset: hex:0x00; |
+0x00000a78 Register(32 bit) cdr_ffe_err_level_frac_set15_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea78 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_err_level_frac_set15_p3 | cdr_ffe_err_level_frac_set15_p1 | cdr_ffe_err_level_frac_set15_m1 | cdr_ffe_err_level_frac_set15_m3 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_err_level_frac_set15_p3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_err_level_frac_set15_p1 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_err_level_frac_set15_m1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_err_level_frac_set15_m3 Reset: hex:0x00; |
+0x00000a7c Register(32 bit) cdr_ffe_control_3
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea7c at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0000c03f | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
| Name | - | cdr_ffe_init_val_w1 | cdr_ffe_tap_min_w1 | cdr_ffe_tap_max_w1 | ||||||||||||||||||||||||||||
| Access | - | RW | RW | RW | ||||||||||||||||||||||||||||
| [23:16] RW |
cdr_ffe_init_val_w1 Reset: hex:0x00; |
| [15:08] RW |
cdr_ffe_tap_min_w1 Reset: hex:0xc0; |
| [07:00] RW |
cdr_ffe_tap_max_w1 Reset: hex:0x3f; |
+0x00000a80 Register(32 bit) cdr_ffe_pre3_set0to3
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea80 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_pre3_coeff_set3 | - | cdr_ffe_pre3_coeff_set2 | - | cdr_ffe_pre3_coeff_set1 | - | cdr_ffe_pre3_coeff_set0 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
cdr_ffe_pre3_coeff_set3 Reset: hex:0x00; |
| [21:16] RW/V |
cdr_ffe_pre3_coeff_set2 Reset: hex:0x00; |
| [13:08] RW/V |
cdr_ffe_pre3_coeff_set1 Reset: hex:0x00; |
| [05:00] RW/V |
cdr_ffe_pre3_coeff_set0 Reset: hex:0x00; |
+0x00000a84 Register(32 bit) cdr_ffe_pre3_set4to7
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea84 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_pre3_coeff_set7 | - | cdr_ffe_pre3_coeff_set6 | - | cdr_ffe_pre3_coeff_set5 | - | cdr_ffe_pre3_coeff_set4 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
cdr_ffe_pre3_coeff_set7 Reset: hex:0x00; |
| [21:16] RW/V |
cdr_ffe_pre3_coeff_set6 Reset: hex:0x00; |
| [13:08] RW/V |
cdr_ffe_pre3_coeff_set5 Reset: hex:0x00; |
| [05:00] RW/V |
cdr_ffe_pre3_coeff_set4 Reset: hex:0x00; |
+0x00000a88 Register(32 bit) cdr_ffe_pre3_set8to11
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea88 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_pre3_coeff_set11 | - | cdr_ffe_pre3_coeff_set10 | - | cdr_ffe_pre3_coeff_set9 | - | cdr_ffe_pre3_coeff_set8 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
cdr_ffe_pre3_coeff_set11 Reset: hex:0x00; |
| [21:16] RW/V |
cdr_ffe_pre3_coeff_set10 Reset: hex:0x00; |
| [13:08] RW/V |
cdr_ffe_pre3_coeff_set9 Reset: hex:0x00; |
| [05:00] RW/V |
cdr_ffe_pre3_coeff_set8 Reset: hex:0x00; |
+0x00000a8c Register(32 bit) cdr_ffe_pre3_set12to15
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea8c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_pre3_coeff_set15 | - | cdr_ffe_pre3_coeff_set14 | - | cdr_ffe_pre3_coeff_set13 | - | cdr_ffe_pre3_coeff_set12 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
cdr_ffe_pre3_coeff_set15 Reset: hex:0x00; |
| [21:16] RW/V |
cdr_ffe_pre3_coeff_set14 Reset: hex:0x00; |
| [13:08] RW/V |
cdr_ffe_pre3_coeff_set13 Reset: hex:0x00; |
| [05:00] RW/V |
cdr_ffe_pre3_coeff_set12 Reset: hex:0x00; |
+0x00000a90 Register(32 bit) cdr_ffe_pre2_set0to3
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea90 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_pre2_coeff_set3 | - | cdr_ffe_pre2_coeff_set2 | - | cdr_ffe_pre2_coeff_set1 | - | cdr_ffe_pre2_coeff_set0 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
cdr_ffe_pre2_coeff_set3 Reset: hex:0x00; |
| [21:16] RW/V |
cdr_ffe_pre2_coeff_set2 Reset: hex:0x00; |
| [13:08] RW/V |
cdr_ffe_pre2_coeff_set1 Reset: hex:0x00; |
| [05:00] RW/V |
cdr_ffe_pre2_coeff_set0 Reset: hex:0x00; |
+0x00000a94 Register(32 bit) cdr_ffe_pre2_set4to7
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea94 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_pre2_coeff_set7 | - | cdr_ffe_pre2_coeff_set6 | - | cdr_ffe_pre2_coeff_set5 | - | cdr_ffe_pre2_coeff_set4 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
cdr_ffe_pre2_coeff_set7 Reset: hex:0x00; |
| [21:16] RW/V |
cdr_ffe_pre2_coeff_set6 Reset: hex:0x00; |
| [13:08] RW/V |
cdr_ffe_pre2_coeff_set5 Reset: hex:0x00; |
| [05:00] RW/V |
cdr_ffe_pre2_coeff_set4 Reset: hex:0x00; |
+0x00000a98 Register(32 bit) cdr_ffe_pre2_set8to11
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea98 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_pre2_coeff_set11 | - | cdr_ffe_pre2_coeff_set10 | - | cdr_ffe_pre2_coeff_set9 | - | cdr_ffe_pre2_coeff_set8 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
cdr_ffe_pre2_coeff_set11 Reset: hex:0x00; |
| [21:16] RW/V |
cdr_ffe_pre2_coeff_set10 Reset: hex:0x00; |
| [13:08] RW/V |
cdr_ffe_pre2_coeff_set9 Reset: hex:0x00; |
| [05:00] RW/V |
cdr_ffe_pre2_coeff_set8 Reset: hex:0x00; |
+0x00000a9c Register(32 bit) cdr_ffe_pre2_set12to15
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ea9c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_pre2_coeff_set15 | - | cdr_ffe_pre2_coeff_set14 | - | cdr_ffe_pre2_coeff_set13 | - | cdr_ffe_pre2_coeff_set12 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
cdr_ffe_pre2_coeff_set15 Reset: hex:0x00; |
| [21:16] RW/V |
cdr_ffe_pre2_coeff_set14 Reset: hex:0x00; |
| [13:08] RW/V |
cdr_ffe_pre2_coeff_set13 Reset: hex:0x00; |
| [05:00] RW/V |
cdr_ffe_pre2_coeff_set12 Reset: hex:0x00; |
+0x00000aa0 Register(32 bit) cdr_ffe_post2_set0to3
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eaa0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post2_coeff_set3 | cdr_ffe_post2_coeff_set2 | cdr_ffe_post2_coeff_set1 | cdr_ffe_post2_coeff_set0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post2_coeff_set3 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post2_coeff_set2 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post2_coeff_set1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post2_coeff_set0 Reset: hex:0x00; |
+0x00000aa4 Register(32 bit) cdr_ffe_post2_set4to7
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eaa4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post2_coeff_set7 | cdr_ffe_post2_coeff_set6 | cdr_ffe_post2_coeff_set5 | cdr_ffe_post2_coeff_set4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post2_coeff_set7 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post2_coeff_set6 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post2_coeff_set5 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post2_coeff_set4 Reset: hex:0x00; |
+0x00000aa8 Register(32 bit) cdr_ffe_post2_set8to11
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eaa8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post2_coeff_set11 | cdr_ffe_post2_coeff_set10 | cdr_ffe_post2_coeff_set9 | cdr_ffe_post2_coeff_set8 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post2_coeff_set11 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post2_coeff_set10 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post2_coeff_set9 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post2_coeff_set8 Reset: hex:0x00; |
+0x00000aac Register(32 bit) cdr_ffe_post2_set12to15
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eaac at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post2_coeff_set15 | cdr_ffe_post2_coeff_set14 | cdr_ffe_post2_coeff_set13 | cdr_ffe_post2_coeff_set12 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post2_coeff_set15 Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post2_coeff_set14 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post2_coeff_set13 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post2_coeff_set12 Reset: hex:0x00; |
+0x00000ab0 Register(32 bit) cdr_ffe_post3_set0to3
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eab0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_post3_coeff_set3 | - | cdr_ffe_post3_coeff_set2 | - | cdr_ffe_post3_coeff_set1 | - | cdr_ffe_post3_coeff_set0 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
cdr_ffe_post3_coeff_set3 Reset: hex:0x00; |
| [21:16] RW/V |
cdr_ffe_post3_coeff_set2 Reset: hex:0x00; |
| [13:08] RW/V |
cdr_ffe_post3_coeff_set1 Reset: hex:0x00; |
| [05:00] RW/V |
cdr_ffe_post3_coeff_set0 Reset: hex:0x00; |
+0x00000ab4 Register(32 bit) cdr_ffe_post3_set4to7
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eab4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_post3_coeff_set7 | - | cdr_ffe_post3_coeff_set6 | - | cdr_ffe_post3_coeff_set5 | - | cdr_ffe_post3_coeff_set4 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
cdr_ffe_post3_coeff_set7 Reset: hex:0x00; |
| [21:16] RW/V |
cdr_ffe_post3_coeff_set6 Reset: hex:0x00; |
| [13:08] RW/V |
cdr_ffe_post3_coeff_set5 Reset: hex:0x00; |
| [05:00] RW/V |
cdr_ffe_post3_coeff_set4 Reset: hex:0x00; |
+0x00000ab8 Register(32 bit) cdr_ffe_post3_set8to11
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eab8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_post3_coeff_set11 | - | cdr_ffe_post3_coeff_set10 | - | cdr_ffe_post3_coeff_set9 | - | cdr_ffe_post3_coeff_set8 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
cdr_ffe_post3_coeff_set11 Reset: hex:0x00; |
| [21:16] RW/V |
cdr_ffe_post3_coeff_set10 Reset: hex:0x00; |
| [13:08] RW/V |
cdr_ffe_post3_coeff_set9 Reset: hex:0x00; |
| [05:00] RW/V |
cdr_ffe_post3_coeff_set8 Reset: hex:0x00; |
+0x00000abc Register(32 bit) cdr_ffe_post3_set12to15
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eabc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_post3_coeff_set15 | - | cdr_ffe_post3_coeff_set14 | - | cdr_ffe_post3_coeff_set13 | - | cdr_ffe_post3_coeff_set12 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
cdr_ffe_post3_coeff_set15 Reset: hex:0x00; |
| [21:16] RW/V |
cdr_ffe_post3_coeff_set14 Reset: hex:0x00; |
| [13:08] RW/V |
cdr_ffe_post3_coeff_set13 Reset: hex:0x00; |
| [05:00] RW/V |
cdr_ffe_post3_coeff_set12 Reset: hex:0x00; |
+0x00000ac0 Register(32 bit) cdr_ffe_post4_set0to3
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eac0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_post4_coeff_set3 | - | cdr_ffe_post4_coeff_set2 | - | cdr_ffe_post4_coeff_set1 | - | cdr_ffe_post4_coeff_set0 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
cdr_ffe_post4_coeff_set3 Reset: hex:0x00; |
| [21:16] RW/V |
cdr_ffe_post4_coeff_set2 Reset: hex:0x00; |
| [13:08] RW/V |
cdr_ffe_post4_coeff_set1 Reset: hex:0x00; |
| [05:00] RW/V |
cdr_ffe_post4_coeff_set0 Reset: hex:0x00; |
+0x00000ac4 Register(32 bit) cdr_ffe_post4_set4to7
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eac4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_post4_coeff_set7 | - | cdr_ffe_post4_coeff_set6 | - | cdr_ffe_post4_coeff_set5 | - | cdr_ffe_post4_coeff_set4 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
cdr_ffe_post4_coeff_set7 Reset: hex:0x00; |
| [21:16] RW/V |
cdr_ffe_post4_coeff_set6 Reset: hex:0x00; |
| [13:08] RW/V |
cdr_ffe_post4_coeff_set5 Reset: hex:0x00; |
| [05:00] RW/V |
cdr_ffe_post4_coeff_set4 Reset: hex:0x00; |
+0x00000ac8 Register(32 bit) cdr_ffe_post4_set8to11
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eac8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_post4_coeff_set11 | - | cdr_ffe_post4_coeff_set10 | - | cdr_ffe_post4_coeff_set9 | - | cdr_ffe_post4_coeff_set8 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
cdr_ffe_post4_coeff_set11 Reset: hex:0x00; |
| [21:16] RW/V |
cdr_ffe_post4_coeff_set10 Reset: hex:0x00; |
| [13:08] RW/V |
cdr_ffe_post4_coeff_set9 Reset: hex:0x00; |
| [05:00] RW/V |
cdr_ffe_post4_coeff_set8 Reset: hex:0x00; |
+0x00000acc Register(32 bit) cdr_ffe_post4_set12to15
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eacc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xc0c0c0c0 | ||
| Undefined | 0xc0c0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_post4_coeff_set15 | - | cdr_ffe_post4_coeff_set14 | - | cdr_ffe_post4_coeff_set13 | - | cdr_ffe_post4_coeff_set12 | ||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||
| [29:24] RW/V |
cdr_ffe_post4_coeff_set15 Reset: hex:0x00; |
| [21:16] RW/V |
cdr_ffe_post4_coeff_set14 Reset: hex:0x00; |
| [13:08] RW/V |
cdr_ffe_post4_coeff_set13 Reset: hex:0x00; |
| [05:00] RW/V |
cdr_ffe_post4_coeff_set12 Reset: hex:0x00; |
+0x00000ad0 Register(32 bit) cdr_ffe_pre3_set0to3_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ead0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_pre3_coeff_set3_frac | cdr_ffe_pre3_coeff_set2_frac | cdr_ffe_pre3_coeff_set1_frac | cdr_ffe_pre3_coeff_set0_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_pre3_coeff_set3_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_pre3_coeff_set2_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_pre3_coeff_set1_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_pre3_coeff_set0_frac Reset: hex:0x00; |
+0x00000ad4 Register(32 bit) cdr_ffe_pre3_set4to7_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ead4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_pre3_coeff_set7_frac | cdr_ffe_pre3_coeff_set6_frac | cdr_ffe_pre3_coeff_set5_frac | cdr_ffe_pre3_coeff_set4_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_pre3_coeff_set7_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_pre3_coeff_set6_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_pre3_coeff_set5_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_pre3_coeff_set4_frac Reset: hex:0x00; |
+0x00000ad8 Register(32 bit) cdr_ffe_pre3_set8to11_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ead8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_pre3_coeff_set11_frac | cdr_ffe_pre3_coeff_set10_frac | cdr_ffe_pre3_coeff_set9_frac | cdr_ffe_pre3_coeff_set8_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_pre3_coeff_set11_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_pre3_coeff_set10_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_pre3_coeff_set9_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_pre3_coeff_set8_frac Reset: hex:0x00; |
+0x00000adc Register(32 bit) cdr_ffe_pre3_set12to15_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eadc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_pre3_coeff_set15_frac | cdr_ffe_pre3_coeff_set14_frac | cdr_ffe_pre3_coeff_set13_frac | cdr_ffe_pre3_coeff_set12_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_pre3_coeff_set15_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_pre3_coeff_set14_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_pre3_coeff_set13_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_pre3_coeff_set12_frac Reset: hex:0x00; |
+0x00000ae0 Register(32 bit) cdr_ffe_pre2_set0to3_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eae0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_pre2_coeff_set3_frac | cdr_ffe_pre2_coeff_set2_frac | cdr_ffe_pre2_coeff_set1_frac | cdr_ffe_pre2_coeff_set0_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_pre2_coeff_set3_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_pre2_coeff_set2_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_pre2_coeff_set1_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_pre2_coeff_set0_frac Reset: hex:0x00; |
+0x00000ae4 Register(32 bit) cdr_ffe_pre2_set4to7_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eae4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_pre2_coeff_set7_frac | cdr_ffe_pre2_coeff_set6_frac | cdr_ffe_pre2_coeff_set5_frac | cdr_ffe_pre2_coeff_set4_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_pre2_coeff_set7_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_pre2_coeff_set6_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_pre2_coeff_set5_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_pre2_coeff_set4_frac Reset: hex:0x00; |
+0x00000ae8 Register(32 bit) cdr_ffe_pre2_set8to11_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eae8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_pre2_coeff_set11_frac | cdr_ffe_pre2_coeff_set10_frac | cdr_ffe_pre2_coeff_set9_frac | cdr_ffe_pre2_coeff_set8_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_pre2_coeff_set11_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_pre2_coeff_set10_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_pre2_coeff_set9_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_pre2_coeff_set8_frac Reset: hex:0x00; |
+0x00000aec Register(32 bit) cdr_ffe_pre2_set12to15_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eaec at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_pre2_coeff_set15_frac | cdr_ffe_pre2_coeff_set14_frac | cdr_ffe_pre2_coeff_set13_frac | cdr_ffe_pre2_coeff_set12_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_pre2_coeff_set15_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_pre2_coeff_set14_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_pre2_coeff_set13_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_pre2_coeff_set12_frac Reset: hex:0x00; |
+0x00000af0 Register(32 bit) cdr_ffe_post2_set0to3_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eaf0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post2_coeff_set3_frac | cdr_ffe_post2_coeff_set2_frac | cdr_ffe_post2_coeff_set1_frac | cdr_ffe_post2_coeff_set0_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post2_coeff_set3_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post2_coeff_set2_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post2_coeff_set1_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post2_coeff_set0_frac Reset: hex:0x00; |
+0x00000af4 Register(32 bit) cdr_ffe_post2_set4to7_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eaf4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post2_coeff_set7_frac | cdr_ffe_post2_coeff_set6_frac | cdr_ffe_post2_coeff_set5_frac | cdr_ffe_post2_coeff_set4_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post2_coeff_set7_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post2_coeff_set6_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post2_coeff_set5_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post2_coeff_set4_frac Reset: hex:0x00; |
+0x00000af8 Register(32 bit) cdr_ffe_post2_set8to11_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eaf8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post2_coeff_set11_frac | cdr_ffe_post2_coeff_set10_frac | cdr_ffe_post2_coeff_set9_frac | cdr_ffe_post2_coeff_set8_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post2_coeff_set11_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post2_coeff_set10_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post2_coeff_set9_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post2_coeff_set8_frac Reset: hex:0x00; |
+0x00000afc Register(32 bit) cdr_ffe_post2_set12to15_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eafc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post2_coeff_set15_frac | cdr_ffe_post2_coeff_set14_frac | cdr_ffe_post2_coeff_set13_frac | cdr_ffe_post2_coeff_set12_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post2_coeff_set15_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post2_coeff_set14_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post2_coeff_set13_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post2_coeff_set12_frac Reset: hex:0x00; |
+0x00000b00 Register(32 bit) cdr_ffe_post3_set0to3_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb00 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post3_coeff_set3_frac | cdr_ffe_post3_coeff_set2_frac | cdr_ffe_post3_coeff_set1_frac | cdr_ffe_post3_coeff_set0_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post3_coeff_set3_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post3_coeff_set2_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post3_coeff_set1_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post3_coeff_set0_frac Reset: hex:0x00; |
+0x00000b04 Register(32 bit) cdr_ffe_post3_set4to7_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb04 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post3_coeff_set7_frac | cdr_ffe_post3_coeff_set6_frac | cdr_ffe_post3_coeff_set5_frac | cdr_ffe_post3_coeff_set4_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post3_coeff_set7_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post3_coeff_set6_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post3_coeff_set5_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post3_coeff_set4_frac Reset: hex:0x00; |
+0x00000b08 Register(32 bit) cdr_ffe_post3_set8to11_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb08 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post3_coeff_set11_frac | cdr_ffe_post3_coeff_set10_frac | cdr_ffe_post3_coeff_set9_frac | cdr_ffe_post3_coeff_set8_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post3_coeff_set11_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post3_coeff_set10_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post3_coeff_set9_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post3_coeff_set8_frac Reset: hex:0x00; |
+0x00000b0c Register(32 bit) cdr_ffe_post3_set12to15_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb0c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post3_coeff_set15_frac | cdr_ffe_post3_coeff_set14_frac | cdr_ffe_post3_coeff_set13_frac | cdr_ffe_post3_coeff_set12_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post3_coeff_set15_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post3_coeff_set14_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post3_coeff_set13_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post3_coeff_set12_frac Reset: hex:0x00; |
+0x00000b10 Register(32 bit) cdr_ffe_post4_set0to3_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb10 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post4_coeff_set3_frac | cdr_ffe_post4_coeff_set2_frac | cdr_ffe_post4_coeff_set1_frac | cdr_ffe_post4_coeff_set0_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post4_coeff_set3_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post4_coeff_set2_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post4_coeff_set1_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post4_coeff_set0_frac Reset: hex:0x00; |
+0x00000b14 Register(32 bit) cdr_ffe_post4_set4to7_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb14 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post4_coeff_set7_frac | cdr_ffe_post4_coeff_set6_frac | cdr_ffe_post4_coeff_set5_frac | cdr_ffe_post4_coeff_set4_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post4_coeff_set7_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post4_coeff_set6_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post4_coeff_set5_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post4_coeff_set4_frac Reset: hex:0x00; |
+0x00000b18 Register(32 bit) cdr_ffe_post4_set8to11_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb18 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post4_coeff_set11_frac | cdr_ffe_post4_coeff_set10_frac | cdr_ffe_post4_coeff_set9_frac | cdr_ffe_post4_coeff_set8_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post4_coeff_set11_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post4_coeff_set10_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post4_coeff_set9_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post4_coeff_set8_frac Reset: hex:0x00; |
+0x00000b1c Register(32 bit) cdr_ffe_post4_set12to15_frac
Rx SAR Array valid
Rx SAR Array valid
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb1c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | cdr_ffe_post4_coeff_set15_frac | cdr_ffe_post4_coeff_set14_frac | cdr_ffe_post4_coeff_set13_frac | cdr_ffe_post4_coeff_set12_frac | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
cdr_ffe_post4_coeff_set15_frac Reset: hex:0x00; |
| [23:16] RW/V |
cdr_ffe_post4_coeff_set14_frac Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_post4_coeff_set13_frac Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_post4_coeff_set12_frac Reset: hex:0x00; |
+0x00000b20 Register(32 bit) saturation_status_4
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb20 at NOC.jesd__axi (Mem)
Access RO/C/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xffffff80 | ||
| Undefined | 0xffffff80 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_tap_post4_sat | cdr_ffe_tap_post3_sat | cdr_ffe_tap_post2_sat | cdr_ffe_tap_post1_sat | cdr_ffe_tap_pre1_sat | cdr_ffe_tap_pre2_sat | cdr_ffe_tap_pre3_sat | ||||||||||||||||||||||||
| Access | - | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | ||||||||||||||||||||||||
| [06:06] RO/C/V |
cdr_ffe_tap_post4_sat Reset: hex:0x0; |
| [05:05] RO/C/V |
cdr_ffe_tap_post3_sat Reset: hex:0x0; |
| [04:04] RO/C/V |
cdr_ffe_tap_post2_sat Reset: hex:0x0; |
| [03:03] RO/C/V |
cdr_ffe_tap_post1_sat Reset: hex:0x0; |
| [02:02] RO/C/V |
cdr_ffe_tap_pre1_sat Reset: hex:0x0; |
| [01:01] RO/C/V |
cdr_ffe_tap_pre2_sat Reset: hex:0x0; |
| [00:00] RO/C/V |
cdr_ffe_tap_pre3_sat Reset: hex:0x0; |
+0x00000b24 Register(32 bit) affe_if_control_0
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb24 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xfffffffc | ||
| Undefined | 0xfffffffc | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 |
| Name | - | affe_taps_backup_load | affe_taps_backup | |||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | |||||||||||||||||||||||||||||
| [01:01] RW/V |
affe_taps_backup_load Reset: hex:0x0; |
| [00:00] RW/V |
affe_taps_backup Reset: hex:0x0; |
+0x00000b28 Register(32 bit) ops_taps_b0_sar_0to3
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb28 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b0_g0_sar3 | ops_taps_b0_g0_sar2 | ops_taps_b0_g0_sar1 | ops_taps_b0_g0_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b0_g0_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b0_g0_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b0_g0_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b0_g0_sar0 Reset: hex:0x00; |
+0x00000b2c Register(32 bit) ops_taps_b0_sar_4to7
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb2c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b0_g0_sar7 | ops_taps_b0_g0_sar6 | ops_taps_b0_g0_sar5 | ops_taps_b0_g0_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b0_g0_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b0_g0_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b0_g0_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b0_g0_sar4 Reset: hex:0x00; |
+0x00000b30 Register(32 bit) ops_taps_b0_sar_8to11
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb30 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b0_g1_sar3 | ops_taps_b0_g1_sar2 | ops_taps_b0_g1_sar1 | ops_taps_b0_g1_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b0_g1_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b0_g1_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b0_g1_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b0_g1_sar0 Reset: hex:0x00; |
+0x00000b34 Register(32 bit) ops_taps_b0_sar_12to15
placeholder
placeholder
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb34 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b0_g1_sar7 | ops_taps_b0_g1_sar6 | ops_taps_b0_g1_sar5 | ops_taps_b0_g1_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b0_g1_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b0_g1_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b0_g1_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b0_g1_sar4 Reset: hex:0x00; |
+0x00000b38 Register(32 bit) ops_taps_b0_sar_16to19
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb38 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b0_g2_sar3 | ops_taps_b0_g2_sar2 | ops_taps_b0_g2_sar1 | ops_taps_b0_g2_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b0_g2_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b0_g2_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b0_g2_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b0_g2_sar0 Reset: hex:0x00; |
+0x00000b3c Register(32 bit) ops_taps_b0_sar_20to23
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb3c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b0_g2_sar7 | ops_taps_b0_g2_sar6 | ops_taps_b0_g2_sar5 | ops_taps_b0_g2_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b0_g2_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b0_g2_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b0_g2_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b0_g2_sar4 Reset: hex:0x00; |
+0x00000b40 Register(32 bit) ops_taps_b0_sar_24to27
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb40 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b0_g3_sar3 | ops_taps_b0_g3_sar2 | ops_taps_b0_g3_sar1 | ops_taps_b0_g3_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b0_g3_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b0_g3_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b0_g3_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b0_g3_sar0 Reset: hex:0x00; |
+0x00000b44 Register(32 bit) ops_taps_b0_sar_28to31
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb44 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b0_g3_sar7 | ops_taps_b0_g3_sar6 | ops_taps_b0_g3_sar5 | ops_taps_b0_g3_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b0_g3_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b0_g3_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b0_g3_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b0_g3_sar4 Reset: hex:0x00; |
+0x00000b48 Register(32 bit) ops_taps_b0_sar_32to35
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb48 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b0_g4_sar3 | ops_taps_b0_g4_sar2 | ops_taps_b0_g4_sar1 | ops_taps_b0_g4_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b0_g4_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b0_g4_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b0_g4_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b0_g4_sar0 Reset: hex:0x00; |
+0x00000b4c Register(32 bit) ops_taps_b0_sar_36to39
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb4c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b0_g4_sar7 | ops_taps_b0_g4_sar6 | ops_taps_b0_g4_sar5 | ops_taps_b0_g4_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b0_g4_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b0_g4_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b0_g4_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b0_g4_sar4 Reset: hex:0x00; |
+0x00000b50 Register(32 bit) ops_taps_b0_sar_40to43
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb50 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b0_g5_sar3 | ops_taps_b0_g5_sar2 | ops_taps_b0_g5_sar1 | ops_taps_b0_g5_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b0_g5_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b0_g5_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b0_g5_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b0_g5_sar0 Reset: hex:0x00; |
+0x00000b54 Register(32 bit) ops_taps_b0_sar_44to47
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb54 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b0_g5_sar7 | ops_taps_b0_g5_sar6 | ops_taps_b0_g5_sar5 | ops_taps_b0_g5_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b0_g5_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b0_g5_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b0_g5_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b0_g5_sar4 Reset: hex:0x00; |
+0x00000b58 Register(32 bit) ops_taps_b0_sar_48to51
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb58 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b0_g6_sar3 | ops_taps_b0_g6_sar2 | ops_taps_b0_g6_sar1 | ops_taps_b0_g6_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b0_g6_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b0_g6_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b0_g6_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b0_g6_sar0 Reset: hex:0x00; |
+0x00000b5c Register(32 bit) ops_taps_b0_sar_52to55
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb5c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b0_g6_sar7 | ops_taps_b0_g6_sar6 | ops_taps_b0_g6_sar5 | ops_taps_b0_g6_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b0_g6_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b0_g6_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b0_g6_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b0_g6_sar4 Reset: hex:0x00; |
+0x00000b60 Register(32 bit) ops_taps_b0_sar_56to59
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb60 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b0_g7_sar3 | ops_taps_b0_g7_sar2 | ops_taps_b0_g7_sar1 | ops_taps_b0_g7_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b0_g7_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b0_g7_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b0_g7_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b0_g7_sar0 Reset: hex:0x00; |
+0x00000b64 Register(32 bit) ops_taps_b0_sar_60to63
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb64 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b0_g7_sar7 | ops_taps_b0_g7_sar6 | ops_taps_b0_g7_sar5 | ops_taps_b0_g7_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b0_g7_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b0_g7_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b0_g7_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b0_g7_sar4 Reset: hex:0x00; |
+0x00000b68 Register(32 bit) ops_taps_b1_sar_0to3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb68 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b1_g0_sar3 | ops_taps_b1_g0_sar2 | ops_taps_b1_g0_sar1 | ops_taps_b1_g0_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b1_g0_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b1_g0_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b1_g0_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b1_g0_sar0 Reset: hex:0x00; |
+0x00000b6c Register(32 bit) ops_taps_b1_sar_4to7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb6c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b1_g0_sar7 | ops_taps_b1_g0_sar6 | ops_taps_b1_g0_sar5 | ops_taps_b1_g0_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b1_g0_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b1_g0_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b1_g0_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b1_g0_sar4 Reset: hex:0x00; |
+0x00000b70 Register(32 bit) ops_taps_b1_sar_8to11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb70 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b1_g1_sar3 | ops_taps_b1_g1_sar2 | ops_taps_b1_g1_sar1 | ops_taps_b1_g1_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b1_g1_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b1_g1_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b1_g1_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b1_g1_sar0 Reset: hex:0x00; |
+0x00000b74 Register(32 bit) ops_taps_b1_sar_12to15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb74 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b1_g1_sar7 | ops_taps_b1_g1_sar6 | ops_taps_b1_g1_sar5 | ops_taps_b1_g1_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b1_g1_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b1_g1_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b1_g1_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b1_g1_sar4 Reset: hex:0x00; |
+0x00000b78 Register(32 bit) ops_taps_b1_sar_16to19
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb78 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b1_g2_sar3 | ops_taps_b1_g2_sar2 | ops_taps_b1_g2_sar1 | ops_taps_b1_g2_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b1_g2_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b1_g2_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b1_g2_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b1_g2_sar0 Reset: hex:0x00; |
+0x00000b7c Register(32 bit) ops_taps_b1_sar_20to23
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb7c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b1_g2_sar7 | ops_taps_b1_g2_sar6 | ops_taps_b1_g2_sar5 | ops_taps_b1_g2_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b1_g2_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b1_g2_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b1_g2_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b1_g2_sar4 Reset: hex:0x00; |
+0x00000b80 Register(32 bit) ops_taps_b1_sar_24to27
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb80 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b1_g3_sar3 | ops_taps_b1_g3_sar2 | ops_taps_b1_g3_sar1 | ops_taps_b1_g3_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b1_g3_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b1_g3_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b1_g3_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b1_g3_sar0 Reset: hex:0x00; |
+0x00000b84 Register(32 bit) ops_taps_b1_sar_28to31
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb84 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b1_g3_sar7 | ops_taps_b1_g3_sar6 | ops_taps_b1_g3_sar5 | ops_taps_b1_g3_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b1_g3_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b1_g3_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b1_g3_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b1_g3_sar4 Reset: hex:0x00; |
+0x00000b88 Register(32 bit) ops_taps_b1_sar_32to35
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb88 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b1_g4_sar3 | ops_taps_b1_g4_sar2 | ops_taps_b1_g4_sar1 | ops_taps_b1_g4_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b1_g4_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b1_g4_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b1_g4_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b1_g4_sar0 Reset: hex:0x00; |
+0x00000b8c Register(32 bit) ops_taps_b1_sar_36to39
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb8c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b1_g4_sar7 | ops_taps_b1_g4_sar6 | ops_taps_b1_g4_sar5 | ops_taps_b1_g4_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b1_g4_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b1_g4_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b1_g4_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b1_g4_sar4 Reset: hex:0x00; |
+0x00000b90 Register(32 bit) ops_taps_b1_sar_40to43
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb90 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b1_g5_sar3 | ops_taps_b1_g5_sar2 | ops_taps_b1_g5_sar1 | ops_taps_b1_g5_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b1_g5_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b1_g5_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b1_g5_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b1_g5_sar0 Reset: hex:0x00; |
+0x00000b94 Register(32 bit) ops_taps_b1_sar_44to47
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb94 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b1_g5_sar7 | ops_taps_b1_g5_sar6 | ops_taps_b1_g5_sar5 | ops_taps_b1_g5_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b1_g5_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b1_g5_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b1_g5_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b1_g5_sar4 Reset: hex:0x00; |
+0x00000b98 Register(32 bit) ops_taps_b1_sar_48to51
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb98 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b1_g6_sar3 | ops_taps_b1_g6_sar2 | ops_taps_b1_g6_sar1 | ops_taps_b1_g6_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b1_g6_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b1_g6_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b1_g6_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b1_g6_sar0 Reset: hex:0x00; |
+0x00000b9c Register(32 bit) ops_taps_b1_sar_52to55
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eb9c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b1_g6_sar7 | ops_taps_b1_g6_sar6 | ops_taps_b1_g6_sar5 | ops_taps_b1_g6_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b1_g6_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b1_g6_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b1_g6_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b1_g6_sar4 Reset: hex:0x00; |
+0x00000ba0 Register(32 bit) ops_taps_b1_sar_56to59
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eba0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b1_g7_sar3 | ops_taps_b1_g7_sar2 | ops_taps_b1_g7_sar1 | ops_taps_b1_g7_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b1_g7_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b1_g7_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b1_g7_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b1_g7_sar0 Reset: hex:0x00; |
+0x00000ba4 Register(32 bit) ops_taps_b1_sar_60to63
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eba4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b1_g7_sar7 | ops_taps_b1_g7_sar6 | ops_taps_b1_g7_sar5 | ops_taps_b1_g7_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b1_g7_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b1_g7_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b1_g7_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b1_g7_sar4 Reset: hex:0x00; |
+0x00000ba8 Register(32 bit) ops_taps_b2_sar_0to3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eba8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b2_g0_sar3 | ops_taps_b2_g0_sar2 | ops_taps_b2_g0_sar1 | ops_taps_b2_g0_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b2_g0_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b2_g0_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b2_g0_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b2_g0_sar0 Reset: hex:0x00; |
+0x00000bac Register(32 bit) ops_taps_b2_sar_4to7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebac at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b2_g0_sar7 | ops_taps_b2_g0_sar6 | ops_taps_b2_g0_sar5 | ops_taps_b2_g0_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b2_g0_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b2_g0_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b2_g0_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b2_g0_sar4 Reset: hex:0x00; |
+0x00000bb0 Register(32 bit) ops_taps_b2_sar_8to11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebb0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b2_g1_sar3 | ops_taps_b2_g1_sar2 | ops_taps_b2_g1_sar1 | ops_taps_b2_g1_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b2_g1_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b2_g1_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b2_g1_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b2_g1_sar0 Reset: hex:0x00; |
+0x00000bb4 Register(32 bit) ops_taps_b2_sar_12to15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebb4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b2_g1_sar7 | ops_taps_b2_g1_sar6 | ops_taps_b2_g1_sar5 | ops_taps_b2_g1_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b2_g1_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b2_g1_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b2_g1_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b2_g1_sar4 Reset: hex:0x00; |
+0x00000bb8 Register(32 bit) ops_taps_b2_sar_16to19
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebb8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b2_g2_sar3 | ops_taps_b2_g2_sar2 | ops_taps_b2_g2_sar1 | ops_taps_b2_g2_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b2_g2_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b2_g2_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b2_g2_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b2_g2_sar0 Reset: hex:0x00; |
+0x00000bbc Register(32 bit) ops_taps_b2_sar_20to23
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebbc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b2_g2_sar7 | ops_taps_b2_g2_sar6 | ops_taps_b2_g2_sar5 | ops_taps_b2_g2_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b2_g2_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b2_g2_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b2_g2_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b2_g2_sar4 Reset: hex:0x00; |
+0x00000bc0 Register(32 bit) ops_taps_b2_sar_24to27
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebc0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b2_g3_sar3 | ops_taps_b2_g3_sar2 | ops_taps_b2_g3_sar1 | ops_taps_b2_g3_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b2_g3_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b2_g3_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b2_g3_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b2_g3_sar0 Reset: hex:0x00; |
+0x00000bc4 Register(32 bit) ops_taps_b2_sar_28to31
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebc4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b2_g3_sar7 | ops_taps_b2_g3_sar6 | ops_taps_b2_g3_sar5 | ops_taps_b2_g3_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b2_g3_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b2_g3_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b2_g3_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b2_g3_sar4 Reset: hex:0x00; |
+0x00000bc8 Register(32 bit) ops_taps_b2_sar_32to35
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebc8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b2_g4_sar3 | ops_taps_b2_g4_sar2 | ops_taps_b2_g4_sar1 | ops_taps_b2_g4_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b2_g4_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b2_g4_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b2_g4_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b2_g4_sar0 Reset: hex:0x00; |
+0x00000bcc Register(32 bit) ops_taps_b2_sar_36to39
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebcc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b2_g4_sar7 | ops_taps_b2_g4_sar6 | ops_taps_b2_g4_sar5 | ops_taps_b2_g4_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b2_g4_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b2_g4_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b2_g4_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b2_g4_sar4 Reset: hex:0x00; |
+0x00000bd0 Register(32 bit) ops_taps_b2_sar_40to43
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebd0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b2_g5_sar3 | ops_taps_b2_g5_sar2 | ops_taps_b2_g5_sar1 | ops_taps_b2_g5_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b2_g5_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b2_g5_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b2_g5_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b2_g5_sar0 Reset: hex:0x00; |
+0x00000bd4 Register(32 bit) ops_taps_b2_sar_44to47
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebd4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b2_g5_sar7 | ops_taps_b2_g5_sar6 | ops_taps_b2_g5_sar5 | ops_taps_b2_g5_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b2_g5_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b2_g5_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b2_g5_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b2_g5_sar4 Reset: hex:0x00; |
+0x00000bd8 Register(32 bit) ops_taps_b2_sar_48to51
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebd8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b2_g6_sar3 | ops_taps_b2_g6_sar2 | ops_taps_b2_g6_sar1 | ops_taps_b2_g6_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b2_g6_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b2_g6_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b2_g6_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b2_g6_sar0 Reset: hex:0x00; |
+0x00000bdc Register(32 bit) ops_taps_b2_sar_52to55
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebdc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b2_g6_sar7 | ops_taps_b2_g6_sar6 | ops_taps_b2_g6_sar5 | ops_taps_b2_g6_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b2_g6_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b2_g6_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b2_g6_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b2_g6_sar4 Reset: hex:0x00; |
+0x00000be0 Register(32 bit) ops_taps_b2_sar_56to59
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebe0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b2_g7_sar3 | ops_taps_b2_g7_sar2 | ops_taps_b2_g7_sar1 | ops_taps_b2_g7_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b2_g7_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b2_g7_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b2_g7_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b2_g7_sar0 Reset: hex:0x00; |
+0x00000be4 Register(32 bit) ops_taps_b2_sar_60to63
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebe4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b2_g7_sar7 | ops_taps_b2_g7_sar6 | ops_taps_b2_g7_sar5 | ops_taps_b2_g7_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b2_g7_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b2_g7_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b2_g7_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b2_g7_sar4 Reset: hex:0x00; |
+0x00000be8 Register(32 bit) ops_taps_b3_sar_0to3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebe8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b3_g0_sar3 | ops_taps_b3_g0_sar2 | ops_taps_b3_g0_sar1 | ops_taps_b3_g0_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b3_g0_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b3_g0_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b3_g0_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b3_g0_sar0 Reset: hex:0x00; |
+0x00000bec Register(32 bit) ops_taps_b3_sar_4to7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebec at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b3_g0_sar7 | ops_taps_b3_g0_sar6 | ops_taps_b3_g0_sar5 | ops_taps_b3_g0_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b3_g0_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b3_g0_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b3_g0_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b3_g0_sar4 Reset: hex:0x00; |
+0x00000bf0 Register(32 bit) ops_taps_b3_sar_8to11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebf0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b3_g1_sar3 | ops_taps_b3_g1_sar2 | ops_taps_b3_g1_sar1 | ops_taps_b3_g1_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b3_g1_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b3_g1_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b3_g1_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b3_g1_sar0 Reset: hex:0x00; |
+0x00000bf4 Register(32 bit) ops_taps_b3_sar_12to15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebf4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b3_g1_sar7 | ops_taps_b3_g1_sar6 | ops_taps_b3_g1_sar5 | ops_taps_b3_g1_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b3_g1_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b3_g1_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b3_g1_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b3_g1_sar4 Reset: hex:0x00; |
+0x00000bf8 Register(32 bit) ops_taps_b3_sar_16to19
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebf8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b3_g2_sar3 | ops_taps_b3_g2_sar2 | ops_taps_b3_g2_sar1 | ops_taps_b3_g2_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b3_g2_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b3_g2_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b3_g2_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b3_g2_sar0 Reset: hex:0x00; |
+0x00000bfc Register(32 bit) ops_taps_b3_sar_20to23
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ebfc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b3_g2_sar7 | ops_taps_b3_g2_sar6 | ops_taps_b3_g2_sar5 | ops_taps_b3_g2_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b3_g2_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b3_g2_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b3_g2_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b3_g2_sar4 Reset: hex:0x00; |
+0x00000c00 Register(32 bit) ops_taps_b3_sar_24to27
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec00 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b3_g3_sar3 | ops_taps_b3_g3_sar2 | ops_taps_b3_g3_sar1 | ops_taps_b3_g3_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b3_g3_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b3_g3_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b3_g3_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b3_g3_sar0 Reset: hex:0x00; |
+0x00000c04 Register(32 bit) ops_taps_b3_sar_28to31
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec04 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b3_g3_sar7 | ops_taps_b3_g3_sar6 | ops_taps_b3_g3_sar5 | ops_taps_b3_g3_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b3_g3_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b3_g3_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b3_g3_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b3_g3_sar4 Reset: hex:0x00; |
+0x00000c08 Register(32 bit) ops_taps_b3_sar_32to35
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec08 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b3_g4_sar3 | ops_taps_b3_g4_sar2 | ops_taps_b3_g4_sar1 | ops_taps_b3_g4_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b3_g4_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b3_g4_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b3_g4_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b3_g4_sar0 Reset: hex:0x00; |
+0x00000c0c Register(32 bit) ops_taps_b3_sar_36to39
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec0c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b3_g4_sar7 | ops_taps_b3_g4_sar6 | ops_taps_b3_g4_sar5 | ops_taps_b3_g4_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b3_g4_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b3_g4_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b3_g4_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b3_g4_sar4 Reset: hex:0x00; |
+0x00000c10 Register(32 bit) ops_taps_b3_sar_40to43
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec10 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b3_g5_sar3 | ops_taps_b3_g5_sar2 | ops_taps_b3_g5_sar1 | ops_taps_b3_g5_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b3_g5_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b3_g5_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b3_g5_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b3_g5_sar0 Reset: hex:0x00; |
+0x00000c14 Register(32 bit) ops_taps_b3_sar_44to47
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec14 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b3_g5_sar7 | ops_taps_b3_g5_sar6 | ops_taps_b3_g5_sar5 | ops_taps_b3_g5_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b3_g5_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b3_g5_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b3_g5_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b3_g5_sar4 Reset: hex:0x00; |
+0x00000c18 Register(32 bit) ops_taps_b3_sar_48to51
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec18 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b3_g6_sar3 | ops_taps_b3_g6_sar2 | ops_taps_b3_g6_sar1 | ops_taps_b3_g6_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b3_g6_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b3_g6_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b3_g6_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b3_g6_sar0 Reset: hex:0x00; |
+0x00000c1c Register(32 bit) ops_taps_b3_sar_52to55
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec1c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b3_g6_sar7 | ops_taps_b3_g6_sar6 | ops_taps_b3_g6_sar5 | ops_taps_b3_g6_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b3_g6_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b3_g6_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b3_g6_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b3_g6_sar4 Reset: hex:0x00; |
+0x00000c20 Register(32 bit) ops_taps_b3_sar_56to59
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec20 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b3_g7_sar3 | ops_taps_b3_g7_sar2 | ops_taps_b3_g7_sar1 | ops_taps_b3_g7_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b3_g7_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b3_g7_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b3_g7_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b3_g7_sar0 Reset: hex:0x00; |
+0x00000c24 Register(32 bit) ops_taps_b3_sar_60to63
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec24 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b3_g7_sar7 | ops_taps_b3_g7_sar6 | ops_taps_b3_g7_sar5 | ops_taps_b3_g7_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b3_g7_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b3_g7_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b3_g7_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b3_g7_sar4 Reset: hex:0x00; |
+0x00000c28 Register(32 bit) ops_taps_b4_sar_0to3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec28 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b4_g0_sar3 | ops_taps_b4_g0_sar2 | ops_taps_b4_g0_sar1 | ops_taps_b4_g0_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b4_g0_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b4_g0_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b4_g0_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b4_g0_sar0 Reset: hex:0x00; |
+0x00000c2c Register(32 bit) ops_taps_b4_sar_4to7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec2c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b4_g0_sar7 | ops_taps_b4_g0_sar6 | ops_taps_b4_g0_sar5 | ops_taps_b4_g0_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b4_g0_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b4_g0_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b4_g0_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b4_g0_sar4 Reset: hex:0x00; |
+0x00000c30 Register(32 bit) ops_taps_b4_sar_8to11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec30 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b4_g1_sar3 | ops_taps_b4_g1_sar2 | ops_taps_b4_g1_sar1 | ops_taps_b4_g1_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b4_g1_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b4_g1_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b4_g1_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b4_g1_sar0 Reset: hex:0x00; |
+0x00000c34 Register(32 bit) ops_taps_b4_sar_12to15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec34 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b4_g1_sar7 | ops_taps_b4_g1_sar6 | ops_taps_b4_g1_sar5 | ops_taps_b4_g1_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b4_g1_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b4_g1_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b4_g1_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b4_g1_sar4 Reset: hex:0x00; |
+0x00000c38 Register(32 bit) ops_taps_b4_sar_16to19
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec38 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b4_g2_sar3 | ops_taps_b4_g2_sar2 | ops_taps_b4_g2_sar1 | ops_taps_b4_g2_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b4_g2_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b4_g2_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b4_g2_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b4_g2_sar0 Reset: hex:0x00; |
+0x00000c3c Register(32 bit) ops_taps_b4_sar_20to23
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec3c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b4_g2_sar7 | ops_taps_b4_g2_sar6 | ops_taps_b4_g2_sar5 | ops_taps_b4_g2_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b4_g2_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b4_g2_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b4_g2_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b4_g2_sar4 Reset: hex:0x00; |
+0x00000c40 Register(32 bit) ops_taps_b4_sar_24to27
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec40 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b4_g3_sar3 | ops_taps_b4_g3_sar2 | ops_taps_b4_g3_sar1 | ops_taps_b4_g3_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b4_g3_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b4_g3_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b4_g3_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b4_g3_sar0 Reset: hex:0x00; |
+0x00000c44 Register(32 bit) ops_taps_b4_sar_28to31
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec44 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b4_g3_sar7 | ops_taps_b4_g3_sar6 | ops_taps_b4_g3_sar5 | ops_taps_b4_g3_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b4_g3_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b4_g3_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b4_g3_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b4_g3_sar4 Reset: hex:0x00; |
+0x00000c48 Register(32 bit) ops_taps_b4_sar_32to35
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec48 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b4_g4_sar3 | ops_taps_b4_g4_sar2 | ops_taps_b4_g4_sar1 | ops_taps_b4_g4_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b4_g4_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b4_g4_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b4_g4_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b4_g4_sar0 Reset: hex:0x00; |
+0x00000c4c Register(32 bit) ops_taps_b4_sar_36to39
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec4c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b4_g4_sar7 | ops_taps_b4_g4_sar6 | ops_taps_b4_g4_sar5 | ops_taps_b4_g4_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b4_g4_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b4_g4_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b4_g4_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b4_g4_sar4 Reset: hex:0x00; |
+0x00000c50 Register(32 bit) ops_taps_b4_sar_40to43
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec50 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b4_g5_sar3 | ops_taps_b4_g5_sar2 | ops_taps_b4_g5_sar1 | ops_taps_b4_g5_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b4_g5_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b4_g5_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b4_g5_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b4_g5_sar0 Reset: hex:0x00; |
+0x00000c54 Register(32 bit) ops_taps_b4_sar_44to47
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec54 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b4_g5_sar7 | ops_taps_b4_g5_sar6 | ops_taps_b4_g5_sar5 | ops_taps_b4_g5_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b4_g5_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b4_g5_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b4_g5_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b4_g5_sar4 Reset: hex:0x00; |
+0x00000c58 Register(32 bit) ops_taps_b4_sar_48to51
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec58 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b4_g6_sar3 | ops_taps_b4_g6_sar2 | ops_taps_b4_g6_sar1 | ops_taps_b4_g6_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b4_g6_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b4_g6_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b4_g6_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b4_g6_sar0 Reset: hex:0x00; |
+0x00000c5c Register(32 bit) ops_taps_b4_sar_52to55
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec5c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b4_g6_sar7 | ops_taps_b4_g6_sar6 | ops_taps_b4_g6_sar5 | ops_taps_b4_g6_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b4_g6_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b4_g6_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b4_g6_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b4_g6_sar4 Reset: hex:0x00; |
+0x00000c60 Register(32 bit) ops_taps_b4_sar_56to59
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec60 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b4_g7_sar3 | ops_taps_b4_g7_sar2 | ops_taps_b4_g7_sar1 | ops_taps_b4_g7_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b4_g7_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b4_g7_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b4_g7_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b4_g7_sar0 Reset: hex:0x00; |
+0x00000c64 Register(32 bit) ops_taps_b4_sar_60to63
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec64 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b4_g7_sar7 | ops_taps_b4_g7_sar6 | ops_taps_b4_g7_sar5 | ops_taps_b4_g7_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b4_g7_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b4_g7_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b4_g7_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b4_g7_sar4 Reset: hex:0x00; |
+0x00000c68 Register(32 bit) ops_taps_b5_sar_0to3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec68 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b5_g0_sar3 | ops_taps_b5_g0_sar2 | ops_taps_b5_g0_sar1 | ops_taps_b5_g0_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b5_g0_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b5_g0_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b5_g0_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b5_g0_sar0 Reset: hex:0x00; |
+0x00000c6c Register(32 bit) ops_taps_b5_sar_4to7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec6c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b5_g0_sar7 | ops_taps_b5_g0_sar6 | ops_taps_b5_g0_sar5 | ops_taps_b5_g0_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b5_g0_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b5_g0_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b5_g0_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b5_g0_sar4 Reset: hex:0x00; |
+0x00000c70 Register(32 bit) ops_taps_b5_sar_8to11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec70 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b5_g1_sar3 | ops_taps_b5_g1_sar2 | ops_taps_b5_g1_sar1 | ops_taps_b5_g1_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b5_g1_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b5_g1_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b5_g1_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b5_g1_sar0 Reset: hex:0x00; |
+0x00000c74 Register(32 bit) ops_taps_b5_sar_12to15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec74 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b5_g1_sar7 | ops_taps_b5_g1_sar6 | ops_taps_b5_g1_sar5 | ops_taps_b5_g1_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b5_g1_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b5_g1_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b5_g1_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b5_g1_sar4 Reset: hex:0x00; |
+0x00000c78 Register(32 bit) ops_taps_b5_sar_16to19
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec78 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b5_g2_sar3 | ops_taps_b5_g2_sar2 | ops_taps_b5_g2_sar1 | ops_taps_b5_g2_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b5_g2_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b5_g2_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b5_g2_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b5_g2_sar0 Reset: hex:0x00; |
+0x00000c7c Register(32 bit) ops_taps_b5_sar_20to23
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec7c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b5_g2_sar7 | ops_taps_b5_g2_sar6 | ops_taps_b5_g2_sar5 | ops_taps_b5_g2_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b5_g2_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b5_g2_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b5_g2_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b5_g2_sar4 Reset: hex:0x00; |
+0x00000c80 Register(32 bit) ops_taps_b5_sar_24to27
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec80 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b5_g3_sar3 | ops_taps_b5_g3_sar2 | ops_taps_b5_g3_sar1 | ops_taps_b5_g3_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b5_g3_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b5_g3_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b5_g3_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b5_g3_sar0 Reset: hex:0x00; |
+0x00000c84 Register(32 bit) ops_taps_b5_sar_28to31
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec84 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b5_g3_sar7 | ops_taps_b5_g3_sar6 | ops_taps_b5_g3_sar5 | ops_taps_b5_g3_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b5_g3_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b5_g3_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b5_g3_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b5_g3_sar4 Reset: hex:0x00; |
+0x00000c88 Register(32 bit) ops_taps_b5_sar_32to35
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec88 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b5_g4_sar3 | ops_taps_b5_g4_sar2 | ops_taps_b5_g4_sar1 | ops_taps_b5_g4_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b5_g4_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b5_g4_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b5_g4_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b5_g4_sar0 Reset: hex:0x00; |
+0x00000c8c Register(32 bit) ops_taps_b5_sar_36to39
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec8c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b5_g4_sar7 | ops_taps_b5_g4_sar6 | ops_taps_b5_g4_sar5 | ops_taps_b5_g4_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b5_g4_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b5_g4_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b5_g4_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b5_g4_sar4 Reset: hex:0x00; |
+0x00000c90 Register(32 bit) ops_taps_b5_sar_40to43
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec90 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b5_g5_sar3 | ops_taps_b5_g5_sar2 | ops_taps_b5_g5_sar1 | ops_taps_b5_g5_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b5_g5_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b5_g5_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b5_g5_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b5_g5_sar0 Reset: hex:0x00; |
+0x00000c94 Register(32 bit) ops_taps_b5_sar_44to47
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec94 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b5_g5_sar7 | ops_taps_b5_g5_sar6 | ops_taps_b5_g5_sar5 | ops_taps_b5_g5_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b5_g5_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b5_g5_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b5_g5_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b5_g5_sar4 Reset: hex:0x00; |
+0x00000c98 Register(32 bit) ops_taps_b5_sar_48to51
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec98 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b5_g6_sar3 | ops_taps_b5_g6_sar2 | ops_taps_b5_g6_sar1 | ops_taps_b5_g6_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b5_g6_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b5_g6_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b5_g6_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b5_g6_sar0 Reset: hex:0x00; |
+0x00000c9c Register(32 bit) ops_taps_b5_sar_52to55
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ec9c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b5_g6_sar7 | ops_taps_b5_g6_sar6 | ops_taps_b5_g6_sar5 | ops_taps_b5_g6_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b5_g6_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b5_g6_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b5_g6_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b5_g6_sar4 Reset: hex:0x00; |
+0x00000ca0 Register(32 bit) ops_taps_b5_sar_56to59
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eca0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b5_g7_sar3 | ops_taps_b5_g7_sar2 | ops_taps_b5_g7_sar1 | ops_taps_b5_g7_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b5_g7_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b5_g7_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b5_g7_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b5_g7_sar0 Reset: hex:0x00; |
+0x00000ca4 Register(32 bit) ops_taps_b5_sar_60to63
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eca4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_b5_g7_sar7 | ops_taps_b5_g7_sar6 | ops_taps_b5_g7_sar5 | ops_taps_b5_g7_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_b5_g7_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_b5_g7_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_b5_g7_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_b5_g7_sar4 Reset: hex:0x00; |
+0x00000ca8 Register(32 bit) ops_taps_fra_b0_sar_0to3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eca8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b0_g0_sar3 | ops_taps_fra_b0_g0_sar2 | ops_taps_fra_b0_g0_sar1 | ops_taps_fra_b0_g0_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b0_g0_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b0_g0_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b0_g0_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b0_g0_sar0 Reset: hex:0x00; |
+0x00000cac Register(32 bit) ops_taps_fra_b0_sar_4to7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ecac at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b0_g0_sar7 | ops_taps_fra_b0_g0_sar6 | ops_taps_fra_b0_g0_sar5 | ops_taps_fra_b0_g0_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b0_g0_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b0_g0_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b0_g0_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b0_g0_sar4 Reset: hex:0x00; |
+0x00000cb0 Register(32 bit) ops_taps_fra_b0_sar_8to11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ecb0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b0_g1_sar3 | ops_taps_fra_b0_g1_sar2 | ops_taps_fra_b0_g1_sar1 | ops_taps_fra_b0_g1_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b0_g1_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b0_g1_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b0_g1_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b0_g1_sar0 Reset: hex:0x00; |
+0x00000cb4 Register(32 bit) ops_taps_fra_b0_sar_12to15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ecb4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b0_g1_sar7 | ops_taps_fra_b0_g1_sar6 | ops_taps_fra_b0_g1_sar5 | ops_taps_fra_b0_g1_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b0_g1_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b0_g1_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b0_g1_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b0_g1_sar4 Reset: hex:0x00; |
+0x00000cb8 Register(32 bit) ops_taps_fra_b0_sar_16to19
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ecb8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b0_g2_sar3 | ops_taps_fra_b0_g2_sar2 | ops_taps_fra_b0_g2_sar1 | ops_taps_fra_b0_g2_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b0_g2_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b0_g2_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b0_g2_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b0_g2_sar0 Reset: hex:0x00; |
+0x00000cbc Register(32 bit) ops_taps_fra_b0_sar_20to23
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ecbc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b0_g2_sar7 | ops_taps_fra_b0_g2_sar6 | ops_taps_fra_b0_g2_sar5 | ops_taps_fra_b0_g2_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b0_g2_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b0_g2_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b0_g2_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b0_g2_sar4 Reset: hex:0x00; |
+0x00000cc0 Register(32 bit) ops_taps_fra_b0_sar_24to27
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ecc0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b0_g3_sar3 | ops_taps_fra_b0_g3_sar2 | ops_taps_fra_b0_g3_sar1 | ops_taps_fra_b0_g3_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b0_g3_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b0_g3_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b0_g3_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b0_g3_sar0 Reset: hex:0x00; |
+0x00000cc4 Register(32 bit) ops_taps_fra_b0_sar_28to31
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ecc4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b0_g3_sar7 | ops_taps_fra_b0_g3_sar6 | ops_taps_fra_b0_g3_sar5 | ops_taps_fra_b0_g3_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b0_g3_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b0_g3_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b0_g3_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b0_g3_sar4 Reset: hex:0x00; |
+0x00000cc8 Register(32 bit) ops_taps_fra_b0_sar_32to35
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ecc8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b0_g4_sar3 | ops_taps_fra_b0_g4_sar2 | ops_taps_fra_b0_g4_sar1 | ops_taps_fra_b0_g4_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b0_g4_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b0_g4_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b0_g4_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b0_g4_sar0 Reset: hex:0x00; |
+0x00000ccc Register(32 bit) ops_taps_fra_b0_sar_36to39
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eccc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b0_g4_sar7 | ops_taps_fra_b0_g4_sar6 | ops_taps_fra_b0_g4_sar5 | ops_taps_fra_b0_g4_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b0_g4_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b0_g4_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b0_g4_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b0_g4_sar4 Reset: hex:0x00; |
+0x00000cd0 Register(32 bit) ops_taps_fra_b0_sar_40to43
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ecd0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b0_g5_sar3 | ops_taps_fra_b0_g5_sar2 | ops_taps_fra_b0_g5_sar1 | ops_taps_fra_b0_g5_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b0_g5_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b0_g5_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b0_g5_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b0_g5_sar0 Reset: hex:0x00; |
+0x00000cd4 Register(32 bit) ops_taps_fra_b0_sar_44to47
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ecd4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b0_g5_sar7 | ops_taps_fra_b0_g5_sar6 | ops_taps_fra_b0_g5_sar5 | ops_taps_fra_b0_g5_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b0_g5_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b0_g5_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b0_g5_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b0_g5_sar4 Reset: hex:0x00; |
+0x00000cd8 Register(32 bit) ops_taps_fra_b0_sar_48to51
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ecd8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b0_g6_sar3 | ops_taps_fra_b0_g6_sar2 | ops_taps_fra_b0_g6_sar1 | ops_taps_fra_b0_g6_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b0_g6_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b0_g6_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b0_g6_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b0_g6_sar0 Reset: hex:0x00; |
+0x00000cdc Register(32 bit) ops_taps_fra_b0_sar_52to55
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ecdc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b0_g6_sar7 | ops_taps_fra_b0_g6_sar6 | ops_taps_fra_b0_g6_sar5 | ops_taps_fra_b0_g6_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b0_g6_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b0_g6_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b0_g6_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b0_g6_sar4 Reset: hex:0x00; |
+0x00000ce0 Register(32 bit) ops_taps_fra_b0_sar_56to59
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ece0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b0_g7_sar3 | ops_taps_fra_b0_g7_sar2 | ops_taps_fra_b0_g7_sar1 | ops_taps_fra_b0_g7_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b0_g7_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b0_g7_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b0_g7_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b0_g7_sar0 Reset: hex:0x00; |
+0x00000ce4 Register(32 bit) ops_taps_fra_b0_sar_60to63
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ece4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b0_g7_sar7 | ops_taps_fra_b0_g7_sar6 | ops_taps_fra_b0_g7_sar5 | ops_taps_fra_b0_g7_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b0_g7_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b0_g7_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b0_g7_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b0_g7_sar4 Reset: hex:0x00; |
+0x00000ce8 Register(32 bit) ops_taps_fra_b1_sar_0to3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ece8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b1_g0_sar3 | ops_taps_fra_b1_g0_sar2 | ops_taps_fra_b1_g0_sar1 | ops_taps_fra_b1_g0_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b1_g0_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b1_g0_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b1_g0_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b1_g0_sar0 Reset: hex:0x00; |
+0x00000cec Register(32 bit) ops_taps_fra_b1_sar_4to7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ecec at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b1_g0_sar7 | ops_taps_fra_b1_g0_sar6 | ops_taps_fra_b1_g0_sar5 | ops_taps_fra_b1_g0_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b1_g0_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b1_g0_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b1_g0_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b1_g0_sar4 Reset: hex:0x00; |
+0x00000cf0 Register(32 bit) ops_taps_fra_b1_sar_8to11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ecf0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b1_g1_sar3 | ops_taps_fra_b1_g1_sar2 | ops_taps_fra_b1_g1_sar1 | ops_taps_fra_b1_g1_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b1_g1_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b1_g1_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b1_g1_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b1_g1_sar0 Reset: hex:0x00; |
+0x00000cf4 Register(32 bit) ops_taps_fra_b1_sar_12to15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ecf4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b1_g1_sar7 | ops_taps_fra_b1_g1_sar6 | ops_taps_fra_b1_g1_sar5 | ops_taps_fra_b1_g1_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b1_g1_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b1_g1_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b1_g1_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b1_g1_sar4 Reset: hex:0x00; |
+0x00000cf8 Register(32 bit) ops_taps_fra_b1_sar_16to19
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ecf8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b1_g2_sar3 | ops_taps_fra_b1_g2_sar2 | ops_taps_fra_b1_g2_sar1 | ops_taps_fra_b1_g2_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b1_g2_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b1_g2_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b1_g2_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b1_g2_sar0 Reset: hex:0x00; |
+0x00000cfc Register(32 bit) ops_taps_fra_b1_sar_20to23
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ecfc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b1_g2_sar7 | ops_taps_fra_b1_g2_sar6 | ops_taps_fra_b1_g2_sar5 | ops_taps_fra_b1_g2_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b1_g2_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b1_g2_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b1_g2_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b1_g2_sar4 Reset: hex:0x00; |
+0x00000d00 Register(32 bit) ops_taps_fra_b1_sar_24to27
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed00 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b1_g3_sar3 | ops_taps_fra_b1_g3_sar2 | ops_taps_fra_b1_g3_sar1 | ops_taps_fra_b1_g3_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b1_g3_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b1_g3_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b1_g3_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b1_g3_sar0 Reset: hex:0x00; |
+0x00000d04 Register(32 bit) ops_taps_fra_b1_sar_28to31
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed04 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b1_g3_sar7 | ops_taps_fra_b1_g3_sar6 | ops_taps_fra_b1_g3_sar5 | ops_taps_fra_b1_g3_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b1_g3_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b1_g3_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b1_g3_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b1_g3_sar4 Reset: hex:0x00; |
+0x00000d08 Register(32 bit) ops_taps_fra_b1_sar_32to35
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed08 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b1_g4_sar3 | ops_taps_fra_b1_g4_sar2 | ops_taps_fra_b1_g4_sar1 | ops_taps_fra_b1_g4_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b1_g4_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b1_g4_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b1_g4_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b1_g4_sar0 Reset: hex:0x00; |
+0x00000d0c Register(32 bit) ops_taps_fra_b1_sar_36to39
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed0c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b1_g4_sar7 | ops_taps_fra_b1_g4_sar6 | ops_taps_fra_b1_g4_sar5 | ops_taps_fra_b1_g4_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b1_g4_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b1_g4_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b1_g4_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b1_g4_sar4 Reset: hex:0x00; |
+0x00000d10 Register(32 bit) ops_taps_fra_b1_sar_40to43
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed10 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b1_g5_sar3 | ops_taps_fra_b1_g5_sar2 | ops_taps_fra_b1_g5_sar1 | ops_taps_fra_b1_g5_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b1_g5_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b1_g5_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b1_g5_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b1_g5_sar0 Reset: hex:0x00; |
+0x00000d14 Register(32 bit) ops_taps_fra_b1_sar_44to47
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed14 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b1_g5_sar7 | ops_taps_fra_b1_g5_sar6 | ops_taps_fra_b1_g5_sar5 | ops_taps_fra_b1_g5_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b1_g5_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b1_g5_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b1_g5_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b1_g5_sar4 Reset: hex:0x00; |
+0x00000d18 Register(32 bit) ops_taps_fra_b1_sar_48to51
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed18 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b1_g6_sar3 | ops_taps_fra_b1_g6_sar2 | ops_taps_fra_b1_g6_sar1 | ops_taps_fra_b1_g6_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b1_g6_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b1_g6_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b1_g6_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b1_g6_sar0 Reset: hex:0x00; |
+0x00000d1c Register(32 bit) ops_taps_fra_b1_sar_52to55
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed1c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b1_g6_sar7 | ops_taps_fra_b1_g6_sar6 | ops_taps_fra_b1_g6_sar5 | ops_taps_fra_b1_g6_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b1_g6_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b1_g6_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b1_g6_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b1_g6_sar4 Reset: hex:0x00; |
+0x00000d20 Register(32 bit) ops_taps_fra_b1_sar_56to59
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed20 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b1_g7_sar3 | ops_taps_fra_b1_g7_sar2 | ops_taps_fra_b1_g7_sar1 | ops_taps_fra_b1_g7_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b1_g7_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b1_g7_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b1_g7_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b1_g7_sar0 Reset: hex:0x00; |
+0x00000d24 Register(32 bit) ops_taps_fra_b1_sar_60to63
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed24 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b1_g7_sar7 | ops_taps_fra_b1_g7_sar6 | ops_taps_fra_b1_g7_sar5 | ops_taps_fra_b1_g7_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b1_g7_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b1_g7_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b1_g7_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b1_g7_sar4 Reset: hex:0x00; |
+0x00000d28 Register(32 bit) ops_taps_fra_b2_sar_0to3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed28 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b2_g0_sar3 | ops_taps_fra_b2_g0_sar2 | ops_taps_fra_b2_g0_sar1 | ops_taps_fra_b2_g0_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b2_g0_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b2_g0_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b2_g0_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b2_g0_sar0 Reset: hex:0x00; |
+0x00000d2c Register(32 bit) ops_taps_fra_b2_sar_4to7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed2c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b2_g0_sar7 | ops_taps_fra_b2_g0_sar6 | ops_taps_fra_b2_g0_sar5 | ops_taps_fra_b2_g0_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b2_g0_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b2_g0_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b2_g0_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b2_g0_sar4 Reset: hex:0x00; |
+0x00000d30 Register(32 bit) ops_taps_fra_b2_sar_8to11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed30 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b2_g1_sar3 | ops_taps_fra_b2_g1_sar2 | ops_taps_fra_b2_g1_sar1 | ops_taps_fra_b2_g1_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b2_g1_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b2_g1_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b2_g1_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b2_g1_sar0 Reset: hex:0x00; |
+0x00000d34 Register(32 bit) ops_taps_fra_b2_sar_12to15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed34 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b2_g1_sar7 | ops_taps_fra_b2_g1_sar6 | ops_taps_fra_b2_g1_sar5 | ops_taps_fra_b2_g1_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b2_g1_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b2_g1_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b2_g1_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b2_g1_sar4 Reset: hex:0x00; |
+0x00000d38 Register(32 bit) ops_taps_fra_b2_sar_16to19
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed38 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b2_g2_sar3 | ops_taps_fra_b2_g2_sar2 | ops_taps_fra_b2_g2_sar1 | ops_taps_fra_b2_g2_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b2_g2_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b2_g2_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b2_g2_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b2_g2_sar0 Reset: hex:0x00; |
+0x00000d3c Register(32 bit) ops_taps_fra_b2_sar_20to23
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed3c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b2_g2_sar7 | ops_taps_fra_b2_g2_sar6 | ops_taps_fra_b2_g2_sar5 | ops_taps_fra_b2_g2_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b2_g2_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b2_g2_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b2_g2_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b2_g2_sar4 Reset: hex:0x00; |
+0x00000d40 Register(32 bit) ops_taps_fra_b2_sar_24to27
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed40 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b2_g3_sar3 | ops_taps_fra_b2_g3_sar2 | ops_taps_fra_b2_g3_sar1 | ops_taps_fra_b2_g3_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b2_g3_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b2_g3_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b2_g3_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b2_g3_sar0 Reset: hex:0x00; |
+0x00000d44 Register(32 bit) ops_taps_fra_b2_sar_28to31
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed44 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b2_g3_sar7 | ops_taps_fra_b2_g3_sar6 | ops_taps_fra_b2_g3_sar5 | ops_taps_fra_b2_g3_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b2_g3_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b2_g3_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b2_g3_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b2_g3_sar4 Reset: hex:0x00; |
+0x00000d48 Register(32 bit) ops_taps_fra_b2_sar_32to35
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed48 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b2_g4_sar3 | ops_taps_fra_b2_g4_sar2 | ops_taps_fra_b2_g4_sar1 | ops_taps_fra_b2_g4_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b2_g4_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b2_g4_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b2_g4_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b2_g4_sar0 Reset: hex:0x00; |
+0x00000d4c Register(32 bit) ops_taps_fra_b2_sar_36to39
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed4c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b2_g4_sar7 | ops_taps_fra_b2_g4_sar6 | ops_taps_fra_b2_g4_sar5 | ops_taps_fra_b2_g4_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b2_g4_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b2_g4_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b2_g4_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b2_g4_sar4 Reset: hex:0x00; |
+0x00000d50 Register(32 bit) ops_taps_fra_b2_sar_40to43
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed50 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b2_g5_sar3 | ops_taps_fra_b2_g5_sar2 | ops_taps_fra_b2_g5_sar1 | ops_taps_fra_b2_g5_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b2_g5_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b2_g5_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b2_g5_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b2_g5_sar0 Reset: hex:0x00; |
+0x00000d54 Register(32 bit) ops_taps_fra_b2_sar_44to47
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed54 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b2_g5_sar7 | ops_taps_fra_b2_g5_sar6 | ops_taps_fra_b2_g5_sar5 | ops_taps_fra_b2_g5_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b2_g5_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b2_g5_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b2_g5_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b2_g5_sar4 Reset: hex:0x00; |
+0x00000d58 Register(32 bit) ops_taps_fra_b2_sar_48to51
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed58 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b2_g6_sar3 | ops_taps_fra_b2_g6_sar2 | ops_taps_fra_b2_g6_sar1 | ops_taps_fra_b2_g6_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b2_g6_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b2_g6_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b2_g6_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b2_g6_sar0 Reset: hex:0x00; |
+0x00000d5c Register(32 bit) ops_taps_fra_b2_sar_52to55
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed5c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b2_g6_sar7 | ops_taps_fra_b2_g6_sar6 | ops_taps_fra_b2_g6_sar5 | ops_taps_fra_b2_g6_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b2_g6_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b2_g6_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b2_g6_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b2_g6_sar4 Reset: hex:0x00; |
+0x00000d60 Register(32 bit) ops_taps_fra_b2_sar_56to59
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed60 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b2_g7_sar3 | ops_taps_fra_b2_g7_sar2 | ops_taps_fra_b2_g7_sar1 | ops_taps_fra_b2_g7_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b2_g7_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b2_g7_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b2_g7_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b2_g7_sar0 Reset: hex:0x00; |
+0x00000d64 Register(32 bit) ops_taps_fra_b2_sar_60to63
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed64 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b2_g7_sar7 | ops_taps_fra_b2_g7_sar6 | ops_taps_fra_b2_g7_sar5 | ops_taps_fra_b2_g7_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b2_g7_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b2_g7_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b2_g7_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b2_g7_sar4 Reset: hex:0x00; |
+0x00000d68 Register(32 bit) ops_taps_fra_b3_sar_0to3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed68 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b3_g0_sar3 | ops_taps_fra_b3_g0_sar2 | ops_taps_fra_b3_g0_sar1 | ops_taps_fra_b3_g0_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b3_g0_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b3_g0_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b3_g0_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b3_g0_sar0 Reset: hex:0x00; |
+0x00000d6c Register(32 bit) ops_taps_fra_b3_sar_4to7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed6c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b3_g0_sar7 | ops_taps_fra_b3_g0_sar6 | ops_taps_fra_b3_g0_sar5 | ops_taps_fra_b3_g0_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b3_g0_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b3_g0_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b3_g0_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b3_g0_sar4 Reset: hex:0x00; |
+0x00000d70 Register(32 bit) ops_taps_fra_b3_sar_8to11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed70 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b3_g1_sar3 | ops_taps_fra_b3_g1_sar2 | ops_taps_fra_b3_g1_sar1 | ops_taps_fra_b3_g1_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b3_g1_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b3_g1_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b3_g1_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b3_g1_sar0 Reset: hex:0x00; |
+0x00000d74 Register(32 bit) ops_taps_fra_b3_sar_12to15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed74 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b3_g1_sar7 | ops_taps_fra_b3_g1_sar6 | ops_taps_fra_b3_g1_sar5 | ops_taps_fra_b3_g1_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b3_g1_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b3_g1_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b3_g1_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b3_g1_sar4 Reset: hex:0x00; |
+0x00000d78 Register(32 bit) ops_taps_fra_b3_sar_16to19
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed78 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b3_g2_sar3 | ops_taps_fra_b3_g2_sar2 | ops_taps_fra_b3_g2_sar1 | ops_taps_fra_b3_g2_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b3_g2_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b3_g2_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b3_g2_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b3_g2_sar0 Reset: hex:0x00; |
+0x00000d7c Register(32 bit) ops_taps_fra_b3_sar_20to23
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed7c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b3_g2_sar7 | ops_taps_fra_b3_g2_sar6 | ops_taps_fra_b3_g2_sar5 | ops_taps_fra_b3_g2_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b3_g2_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b3_g2_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b3_g2_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b3_g2_sar4 Reset: hex:0x00; |
+0x00000d80 Register(32 bit) ops_taps_fra_b3_sar_24to27
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed80 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b3_g3_sar3 | ops_taps_fra_b3_g3_sar2 | ops_taps_fra_b3_g3_sar1 | ops_taps_fra_b3_g3_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b3_g3_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b3_g3_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b3_g3_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b3_g3_sar0 Reset: hex:0x00; |
+0x00000d84 Register(32 bit) ops_taps_fra_b3_sar_28to31
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed84 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b3_g3_sar7 | ops_taps_fra_b3_g3_sar6 | ops_taps_fra_b3_g3_sar5 | ops_taps_fra_b3_g3_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b3_g3_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b3_g3_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b3_g3_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b3_g3_sar4 Reset: hex:0x00; |
+0x00000d88 Register(32 bit) ops_taps_fra_b3_sar_32to35
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed88 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b3_g4_sar3 | ops_taps_fra_b3_g4_sar2 | ops_taps_fra_b3_g4_sar1 | ops_taps_fra_b3_g4_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b3_g4_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b3_g4_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b3_g4_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b3_g4_sar0 Reset: hex:0x00; |
+0x00000d8c Register(32 bit) ops_taps_fra_b3_sar_36to39
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed8c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b3_g4_sar7 | ops_taps_fra_b3_g4_sar6 | ops_taps_fra_b3_g4_sar5 | ops_taps_fra_b3_g4_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b3_g4_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b3_g4_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b3_g4_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b3_g4_sar4 Reset: hex:0x00; |
+0x00000d90 Register(32 bit) ops_taps_fra_b3_sar_40to43
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed90 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b3_g5_sar3 | ops_taps_fra_b3_g5_sar2 | ops_taps_fra_b3_g5_sar1 | ops_taps_fra_b3_g5_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b3_g5_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b3_g5_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b3_g5_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b3_g5_sar0 Reset: hex:0x00; |
+0x00000d94 Register(32 bit) ops_taps_fra_b3_sar_44to47
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed94 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b3_g5_sar7 | ops_taps_fra_b3_g5_sar6 | ops_taps_fra_b3_g5_sar5 | ops_taps_fra_b3_g5_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b3_g5_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b3_g5_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b3_g5_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b3_g5_sar4 Reset: hex:0x00; |
+0x00000d98 Register(32 bit) ops_taps_fra_b3_sar_48to51
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed98 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b3_g6_sar3 | ops_taps_fra_b3_g6_sar2 | ops_taps_fra_b3_g6_sar1 | ops_taps_fra_b3_g6_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b3_g6_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b3_g6_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b3_g6_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b3_g6_sar0 Reset: hex:0x00; |
+0x00000d9c Register(32 bit) ops_taps_fra_b3_sar_52to55
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ed9c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b3_g6_sar7 | ops_taps_fra_b3_g6_sar6 | ops_taps_fra_b3_g6_sar5 | ops_taps_fra_b3_g6_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b3_g6_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b3_g6_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b3_g6_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b3_g6_sar4 Reset: hex:0x00; |
+0x00000da0 Register(32 bit) ops_taps_fra_b3_sar_56to59
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eda0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b3_g7_sar3 | ops_taps_fra_b3_g7_sar2 | ops_taps_fra_b3_g7_sar1 | ops_taps_fra_b3_g7_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b3_g7_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b3_g7_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b3_g7_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b3_g7_sar0 Reset: hex:0x00; |
+0x00000da4 Register(32 bit) ops_taps_fra_b3_sar_60to63
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eda4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b3_g7_sar7 | ops_taps_fra_b3_g7_sar6 | ops_taps_fra_b3_g7_sar5 | ops_taps_fra_b3_g7_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b3_g7_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b3_g7_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b3_g7_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b3_g7_sar4 Reset: hex:0x00; |
+0x00000da8 Register(32 bit) ops_taps_fra_b4_sar_0to3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eda8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b4_g0_sar3 | ops_taps_fra_b4_g0_sar2 | ops_taps_fra_b4_g0_sar1 | ops_taps_fra_b4_g0_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b4_g0_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b4_g0_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b4_g0_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b4_g0_sar0 Reset: hex:0x00; |
+0x00000dac Register(32 bit) ops_taps_fra_b4_sar_4to7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782edac at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b4_g0_sar7 | ops_taps_fra_b4_g0_sar6 | ops_taps_fra_b4_g0_sar5 | ops_taps_fra_b4_g0_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b4_g0_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b4_g0_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b4_g0_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b4_g0_sar4 Reset: hex:0x00; |
+0x00000db0 Register(32 bit) ops_taps_fra_b4_sar_8to11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782edb0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b4_g1_sar3 | ops_taps_fra_b4_g1_sar2 | ops_taps_fra_b4_g1_sar1 | ops_taps_fra_b4_g1_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b4_g1_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b4_g1_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b4_g1_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b4_g1_sar0 Reset: hex:0x00; |
+0x00000db4 Register(32 bit) ops_taps_fra_b4_sar_12to15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782edb4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b4_g1_sar7 | ops_taps_fra_b4_g1_sar6 | ops_taps_fra_b4_g1_sar5 | ops_taps_fra_b4_g1_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b4_g1_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b4_g1_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b4_g1_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b4_g1_sar4 Reset: hex:0x00; |
+0x00000db8 Register(32 bit) ops_taps_fra_b4_sar_16to19
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782edb8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b4_g2_sar3 | ops_taps_fra_b4_g2_sar2 | ops_taps_fra_b4_g2_sar1 | ops_taps_fra_b4_g2_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b4_g2_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b4_g2_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b4_g2_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b4_g2_sar0 Reset: hex:0x00; |
+0x00000dbc Register(32 bit) ops_taps_fra_b4_sar_20to23
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782edbc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b4_g2_sar7 | ops_taps_fra_b4_g2_sar6 | ops_taps_fra_b4_g2_sar5 | ops_taps_fra_b4_g2_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b4_g2_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b4_g2_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b4_g2_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b4_g2_sar4 Reset: hex:0x00; |
+0x00000dc0 Register(32 bit) ops_taps_fra_b4_sar_24to27
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782edc0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b4_g3_sar3 | ops_taps_fra_b4_g3_sar2 | ops_taps_fra_b4_g3_sar1 | ops_taps_fra_b4_g3_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b4_g3_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b4_g3_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b4_g3_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b4_g3_sar0 Reset: hex:0x00; |
+0x00000dc4 Register(32 bit) ops_taps_fra_b4_sar_28to31
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782edc4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b4_g3_sar7 | ops_taps_fra_b4_g3_sar6 | ops_taps_fra_b4_g3_sar5 | ops_taps_fra_b4_g3_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b4_g3_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b4_g3_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b4_g3_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b4_g3_sar4 Reset: hex:0x00; |
+0x00000dc8 Register(32 bit) ops_taps_fra_b4_sar_32to35
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782edc8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b4_g4_sar3 | ops_taps_fra_b4_g4_sar2 | ops_taps_fra_b4_g4_sar1 | ops_taps_fra_b4_g4_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b4_g4_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b4_g4_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b4_g4_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b4_g4_sar0 Reset: hex:0x00; |
+0x00000dcc Register(32 bit) ops_taps_fra_b4_sar_36to39
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782edcc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b4_g4_sar7 | ops_taps_fra_b4_g4_sar6 | ops_taps_fra_b4_g4_sar5 | ops_taps_fra_b4_g4_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b4_g4_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b4_g4_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b4_g4_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b4_g4_sar4 Reset: hex:0x00; |
+0x00000dd0 Register(32 bit) ops_taps_fra_b4_sar_40to43
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782edd0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b4_g5_sar3 | ops_taps_fra_b4_g5_sar2 | ops_taps_fra_b4_g5_sar1 | ops_taps_fra_b4_g5_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b4_g5_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b4_g5_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b4_g5_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b4_g5_sar0 Reset: hex:0x00; |
+0x00000dd4 Register(32 bit) ops_taps_fra_b4_sar_44to47
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782edd4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b4_g5_sar7 | ops_taps_fra_b4_g5_sar6 | ops_taps_fra_b4_g5_sar5 | ops_taps_fra_b4_g5_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b4_g5_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b4_g5_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b4_g5_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b4_g5_sar4 Reset: hex:0x00; |
+0x00000dd8 Register(32 bit) ops_taps_fra_b4_sar_48to51
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782edd8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b4_g6_sar3 | ops_taps_fra_b4_g6_sar2 | ops_taps_fra_b4_g6_sar1 | ops_taps_fra_b4_g6_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b4_g6_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b4_g6_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b4_g6_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b4_g6_sar0 Reset: hex:0x00; |
+0x00000ddc Register(32 bit) ops_taps_fra_b4_sar_52to55
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eddc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b4_g6_sar7 | ops_taps_fra_b4_g6_sar6 | ops_taps_fra_b4_g6_sar5 | ops_taps_fra_b4_g6_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b4_g6_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b4_g6_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b4_g6_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b4_g6_sar4 Reset: hex:0x00; |
+0x00000de0 Register(32 bit) ops_taps_fra_b4_sar_56to59
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ede0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b4_g7_sar3 | ops_taps_fra_b4_g7_sar2 | ops_taps_fra_b4_g7_sar1 | ops_taps_fra_b4_g7_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b4_g7_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b4_g7_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b4_g7_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b4_g7_sar0 Reset: hex:0x00; |
+0x00000de4 Register(32 bit) ops_taps_fra_b4_sar_60to63
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ede4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b4_g7_sar7 | ops_taps_fra_b4_g7_sar6 | ops_taps_fra_b4_g7_sar5 | ops_taps_fra_b4_g7_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b4_g7_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b4_g7_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b4_g7_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b4_g7_sar4 Reset: hex:0x00; |
+0x00000de8 Register(32 bit) ops_taps_fra_b5_sar_0to3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ede8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b5_g0_sar3 | ops_taps_fra_b5_g0_sar2 | ops_taps_fra_b5_g0_sar1 | ops_taps_fra_b5_g0_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b5_g0_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b5_g0_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b5_g0_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b5_g0_sar0 Reset: hex:0x00; |
+0x00000dec Register(32 bit) ops_taps_fra_b5_sar_4to7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782edec at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b5_g0_sar7 | ops_taps_fra_b5_g0_sar6 | ops_taps_fra_b5_g0_sar5 | ops_taps_fra_b5_g0_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b5_g0_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b5_g0_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b5_g0_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b5_g0_sar4 Reset: hex:0x00; |
+0x00000df0 Register(32 bit) ops_taps_fra_b5_sar_8to11
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782edf0 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b5_g1_sar3 | ops_taps_fra_b5_g1_sar2 | ops_taps_fra_b5_g1_sar1 | ops_taps_fra_b5_g1_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b5_g1_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b5_g1_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b5_g1_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b5_g1_sar0 Reset: hex:0x00; |
+0x00000df4 Register(32 bit) ops_taps_fra_b5_sar_12to15
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782edf4 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b5_g1_sar7 | ops_taps_fra_b5_g1_sar6 | ops_taps_fra_b5_g1_sar5 | ops_taps_fra_b5_g1_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b5_g1_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b5_g1_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b5_g1_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b5_g1_sar4 Reset: hex:0x00; |
+0x00000df8 Register(32 bit) ops_taps_fra_b5_sar_16to19
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782edf8 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b5_g2_sar3 | ops_taps_fra_b5_g2_sar2 | ops_taps_fra_b5_g2_sar1 | ops_taps_fra_b5_g2_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b5_g2_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b5_g2_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b5_g2_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b5_g2_sar0 Reset: hex:0x00; |
+0x00000dfc Register(32 bit) ops_taps_fra_b5_sar_20to23
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782edfc at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b5_g2_sar7 | ops_taps_fra_b5_g2_sar6 | ops_taps_fra_b5_g2_sar5 | ops_taps_fra_b5_g2_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b5_g2_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b5_g2_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b5_g2_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b5_g2_sar4 Reset: hex:0x00; |
+0x00000e00 Register(32 bit) ops_taps_fra_b5_sar_24to27
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee00 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b5_g3_sar3 | ops_taps_fra_b5_g3_sar2 | ops_taps_fra_b5_g3_sar1 | ops_taps_fra_b5_g3_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b5_g3_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b5_g3_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b5_g3_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b5_g3_sar0 Reset: hex:0x00; |
+0x00000e04 Register(32 bit) ops_taps_fra_b5_sar_28to31
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee04 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b5_g3_sar7 | ops_taps_fra_b5_g3_sar6 | ops_taps_fra_b5_g3_sar5 | ops_taps_fra_b5_g3_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b5_g3_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b5_g3_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b5_g3_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b5_g3_sar4 Reset: hex:0x00; |
+0x00000e08 Register(32 bit) ops_taps_fra_b5_sar_32to35
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee08 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b5_g4_sar3 | ops_taps_fra_b5_g4_sar2 | ops_taps_fra_b5_g4_sar1 | ops_taps_fra_b5_g4_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b5_g4_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b5_g4_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b5_g4_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b5_g4_sar0 Reset: hex:0x00; |
+0x00000e0c Register(32 bit) ops_taps_fra_b5_sar_36to39
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee0c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b5_g4_sar7 | ops_taps_fra_b5_g4_sar6 | ops_taps_fra_b5_g4_sar5 | ops_taps_fra_b5_g4_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b5_g4_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b5_g4_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b5_g4_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b5_g4_sar4 Reset: hex:0x00; |
+0x00000e10 Register(32 bit) ops_taps_fra_b5_sar_40to43
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee10 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b5_g5_sar3 | ops_taps_fra_b5_g5_sar2 | ops_taps_fra_b5_g5_sar1 | ops_taps_fra_b5_g5_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b5_g5_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b5_g5_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b5_g5_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b5_g5_sar0 Reset: hex:0x00; |
+0x00000e14 Register(32 bit) ops_taps_fra_b5_sar_44to47
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee14 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b5_g5_sar7 | ops_taps_fra_b5_g5_sar6 | ops_taps_fra_b5_g5_sar5 | ops_taps_fra_b5_g5_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b5_g5_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b5_g5_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b5_g5_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b5_g5_sar4 Reset: hex:0x00; |
+0x00000e18 Register(32 bit) ops_taps_fra_b5_sar_48to51
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee18 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b5_g6_sar3 | ops_taps_fra_b5_g6_sar2 | ops_taps_fra_b5_g6_sar1 | ops_taps_fra_b5_g6_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b5_g6_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b5_g6_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b5_g6_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b5_g6_sar0 Reset: hex:0x00; |
+0x00000e1c Register(32 bit) ops_taps_fra_b5_sar_52to55
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee1c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b5_g6_sar7 | ops_taps_fra_b5_g6_sar6 | ops_taps_fra_b5_g6_sar5 | ops_taps_fra_b5_g6_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b5_g6_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b5_g6_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b5_g6_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b5_g6_sar4 Reset: hex:0x00; |
+0x00000e20 Register(32 bit) ops_taps_fra_b5_sar_56to59
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee20 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b5_g7_sar3 | ops_taps_fra_b5_g7_sar2 | ops_taps_fra_b5_g7_sar1 | ops_taps_fra_b5_g7_sar0 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b5_g7_sar3 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b5_g7_sar2 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b5_g7_sar1 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b5_g7_sar0 Reset: hex:0x00; |
+0x00000e24 Register(32 bit) ops_taps_fra_b5_sar_60to63
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee24 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | ops_taps_fra_b5_g7_sar7 | ops_taps_fra_b5_g7_sar6 | ops_taps_fra_b5_g7_sar5 | ops_taps_fra_b5_g7_sar4 | ||||||||||||||||||||||||||||
| Access | RW/V | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [31:24] RW/V |
ops_taps_fra_b5_g7_sar7 Reset: hex:0x00; |
| [23:16] RW/V |
ops_taps_fra_b5_g7_sar6 Reset: hex:0x00; |
| [15:08] RW/V |
ops_taps_fra_b5_g7_sar5 Reset: hex:0x00; |
| [07:00] RW/V |
ops_taps_fra_b5_g7_sar4 Reset: hex:0x00; |
+0x00000e28 Register(32 bit) ofc_control_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee28 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x000b42d0 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| Name | - | ofc_taps_2 | ofc_taps_1 | ofc_taps_0 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ofc_taps_2 Reset: hex:0x000; |
| [19:10] RW/V |
ofc_taps_1 Reset: hex:0x2d0; |
| [09:00] RW/V |
ofc_taps_0 Reset: hex:0x2d0; |
+0x00000e2c Register(32 bit) ofc_control_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee2c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x1304c000 | |
| Unaffected | 0xc0000000 | ||
| Undefined | 0xc0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ofc_taps_5 | ofc_taps_4 | ofc_taps_3 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [29:20] RW/V |
ofc_taps_5 Reset: hex:0x130; |
| [19:10] RW/V |
ofc_taps_4 Reset: hex:0x130; |
| [09:00] RW/V |
ofc_taps_3 Reset: hex:0x000; |
+0x00000e30 Register(32 bit) ofc_control_6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee30 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ofc_taps_fra_2 | ofc_taps_fra_1 | ofc_taps_fra_0 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [23:16] RW/V |
ofc_taps_fra_2 Reset: hex:0x00; |
| [15:08] RW/V |
ofc_taps_fra_1 Reset: hex:0x00; |
| [07:00] RW/V |
ofc_taps_fra_0 Reset: hex:0x00; |
+0x00000e34 Register(32 bit) ofc_control_7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee34 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | ofc_taps_fra_5 | ofc_taps_fra_4 | ofc_taps_fra_3 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [23:16] RW/V |
ofc_taps_fra_5 Reset: hex:0x00; |
| [15:08] RW/V |
ofc_taps_fra_4 Reset: hex:0x00; |
| [07:00] RW/V |
ofc_taps_fra_3 Reset: hex:0x00; |
+0x00000e38 Register(32 bit) cdr_ffe_ofc_control_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee38 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x0005a168 | |
| Unaffected | 0xe0080200 | ||
| Undefined | 0xe0080200 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | - | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 |
| Name | - | cdr_ffe_ofc_taps_2 | - | cdr_ffe_ofc_taps_1 | - | cdr_ffe_ofc_taps_0 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [28:20] RW/V |
cdr_ffe_ofc_taps_2 Reset: hex:0x000; |
| [18:10] RW/V |
cdr_ffe_ofc_taps_1 Reset: hex:0x168; |
| [08:00] RW/V |
cdr_ffe_ofc_taps_0 Reset: hex:0x168; |
+0x00000e3c Register(32 bit) cdr_ffe_ofc_control_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee3c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x09826000 | |
| Unaffected | 0xe0080200 | ||
| Undefined | 0xe0080200 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_ofc_taps_5 | - | cdr_ffe_ofc_taps_4 | - | cdr_ffe_ofc_taps_3 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [28:20] RW/V |
cdr_ffe_ofc_taps_5 Reset: hex:0x098; |
| [18:10] RW/V |
cdr_ffe_ofc_taps_4 Reset: hex:0x098; |
| [08:00] RW/V |
cdr_ffe_ofc_taps_3 Reset: hex:0x000; |
+0x00000e40 Register(32 bit) cdr_ffe_ofc_control_6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee40 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_ofc_taps_fra_2 | cdr_ffe_ofc_taps_fra_1 | cdr_ffe_ofc_taps_fra_0 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [23:16] RW/V |
cdr_ffe_ofc_taps_fra_2 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_ofc_taps_fra_1 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_ofc_taps_fra_0 Reset: hex:0x00; |
+0x00000e44 Register(32 bit) cdr_ffe_ofc_control_7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee44 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | cdr_ffe_ofc_taps_fra_5 | cdr_ffe_ofc_taps_fra_4 | cdr_ffe_ofc_taps_fra_3 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [23:16] RW/V |
cdr_ffe_ofc_taps_fra_5 Reset: hex:0x00; |
| [15:08] RW/V |
cdr_ffe_ofc_taps_fra_4 Reset: hex:0x00; |
| [07:00] RW/V |
cdr_ffe_ofc_taps_fra_3 Reset: hex:0x00; |
+0x00000e48 Register(32 bit) adcofc_control_4
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee48 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00002d2d | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | - | - | 1 | 0 | 1 | 1 | 0 | 1 | - | - | 1 | 0 | 1 | 1 | 0 | 1 |
| Name | - | adcofc_taps_2 | - | adcofc_taps_1 | - | adcofc_taps_0 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adcofc_taps_2 Reset: hex:0x00; |
| [13:08] RW/V |
adcofc_taps_1 Reset: hex:0x2d; |
| [05:00] RW/V |
adcofc_taps_0 Reset: hex:0x2d; |
+0x00000e4c Register(32 bit) adcofc_control_5
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee4c at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00131300 | |
| Unaffected | 0xffc0c0c0 | ||
| Undefined | 0xffc0c0c0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | 0 | 1 | 0 | 0 | 1 | 1 | - | - | 0 | 1 | 0 | 0 | 1 | 1 | - | - | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | adcofc_taps_5 | - | adcofc_taps_4 | - | adcofc_taps_3 | ||||||||||||||||||||||||||
| Access | - | RW/V | - | RW/V | - | RW/V | ||||||||||||||||||||||||||
| [21:16] RW/V |
adcofc_taps_5 Reset: hex:0x13; |
| [13:08] RW/V |
adcofc_taps_4 Reset: hex:0x13; |
| [05:00] RW/V |
adcofc_taps_3 Reset: hex:0x00; |
+0x00000e50 Register(32 bit) adcofc_control_6
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee50 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | adcofc_taps_fra_2 | adcofc_taps_fra_1 | adcofc_taps_fra_0 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [23:16] RW/V |
adcofc_taps_fra_2 Reset: hex:0x00; |
| [15:08] RW/V |
adcofc_taps_fra_1 Reset: hex:0x00; |
| [07:00] RW/V |
adcofc_taps_fra_0 Reset: hex:0x00; |
+0x00000e54 Register(32 bit) adcofc_control_7
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ee54 at NOC.jesd__axi (Mem)
Access RW/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xff000000 | ||
| Undefined | 0xff000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | adcofc_taps_fra_5 | adcofc_taps_fra_4 | adcofc_taps_fra_3 | ||||||||||||||||||||||||||||
| Access | - | RW/V | RW/V | RW/V | ||||||||||||||||||||||||||||
| [23:16] RW/V |
adcofc_taps_fra_5 Reset: hex:0x00; |
| [15:08] RW/V |
adcofc_taps_fra_4 Reset: hex:0x00; |
| [07:00] RW/V |
adcofc_taps_fra_3 Reset: hex:0x00; |
+0x00000ef8 Register(32 bit) rx_sigdet_venv_ctrl1
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eef8 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | rx_sigdet_voltage_envelope_priority | rx_sigdet_voltage_envelope_los_cnt_clr | rx_sigdet_voltage_envelope_det_cnt_clr | rx_sigdet_voltage_envelope_debounce_los_val | rx_sigdet_voltage_envelope_debounce_det_val | rx_sigdet_voltage_envelope_res_ovrd_val | rx_sigdet_voltage_envelope_res_ovrd_en | rx_sigdet_voltage_envelope_src_ovrd_val | rx_sigdet_voltage_envelope_src_ovrd_en | rx_sigdet_voltage_envelope_stats_max | rx_sigdet_voltage_envelope_iter | rx_sigdet_voltage_envelope_cont_mode | rx_sigdet_voltage_envelope_en | |||||||||||||||||||
| Access | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | RW | |||||||||||||||||||
| [31:31] RW |
rx_sigdet_voltage_envelope_priority Reset: hex:0x0; |
| [30:30] RW |
rx_sigdet_voltage_envelope_los_cnt_clr Reset: hex:0x0; |
| [29:29] RW |
rx_sigdet_voltage_envelope_det_cnt_clr Reset: hex:0x0; |
| [28:26] RW |
rx_sigdet_voltage_envelope_debounce_los_val Reset: hex:0x0; |
| [25:23] RW |
rx_sigdet_voltage_envelope_debounce_det_val Reset: hex:0x0; |
| [22:22] RW |
rx_sigdet_voltage_envelope_res_ovrd_val Reset: hex:0x0; |
| [21:21] RW |
rx_sigdet_voltage_envelope_res_ovrd_en Reset: hex:0x0; |
| [20:19] RW |
rx_sigdet_voltage_envelope_src_ovrd_val Reset: hex:0x0; |
| [18:18] RW |
rx_sigdet_voltage_envelope_src_ovrd_en Reset: hex:0x0; |
| [17:10] RW |
rx_sigdet_voltage_envelope_stats_max Reset: hex:0x00; |
| [09:02] RW |
rx_sigdet_voltage_envelope_iter Reset: hex:0x00; |
| [01:01] RW |
rx_sigdet_voltage_envelope_cont_mode Reset: hex:0x0; |
| [00:00] RW |
rx_sigdet_voltage_envelope_en Reset: hex:0x0; |
+0x00000efc Register(32 bit) rx_sigdet_venv_ctrl2
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782eefc at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | rx_sigdet_voltage_envelope_det_thresh | rx_sigdet_voltage_envelope_det_nlevel | rx_sigdet_voltage_envelope_det_plevel | |||||||||||||||||||||||||||||
| Access | RW | RW | RW | |||||||||||||||||||||||||||||
| [31:18] RW |
rx_sigdet_voltage_envelope_det_thresh Reset: hex:0x0000; |
| [17:09] RW |
rx_sigdet_voltage_envelope_det_nlevel Reset: hex:0x000; |
| [08:00] RW |
rx_sigdet_voltage_envelope_det_plevel Reset: hex:0x000; |
+0x00000f00 Register(32 bit) rx_sigdet_venv_ctrl3
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ef00 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | rx_sigdet_voltage_envelope_los_thresh | rx_sigdet_voltage_envelope_los_nlevel | rx_sigdet_voltage_envelope_los_plevel | |||||||||||||||||||||||||||||
| Access | RW | RW | RW | |||||||||||||||||||||||||||||
| [31:18] RW |
rx_sigdet_voltage_envelope_los_thresh Reset: hex:0x0000; |
| [17:09] RW |
rx_sigdet_voltage_envelope_los_nlevel Reset: hex:0x000; |
| [08:00] RW |
rx_sigdet_voltage_envelope_los_plevel Reset: hex:0x000; |
+0x00000f04 Register(32 bit) rx_sigdet_venv_status
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ef04 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xf0000000 | ||
| Undefined | 0xf0000000 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | - | rx_sigdet_voltage_envelope_los_cnt | rx_sigdet_voltage_envelope_det_cnt | |||||||||||||||||||||||||||||
| Access | - | RO/V | RO/V | |||||||||||||||||||||||||||||
| [27:14] RO/V |
rx_sigdet_voltage_envelope_los_cnt Reset: hex:0x0000; |
| [13:00] RO/V |
rx_sigdet_voltage_envelope_det_cnt Reset: hex:0x0000; |
+0x00000f08 Register(32 bit) rx_sigdet_venv_status_clr
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Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782ef08 at NOC.jesd__axi (Mem)
Access RO/C/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | 0x00000000 | |
| Unaffected | 0xffffffe0 | ||
| Undefined | 0xffffffe0 | ||
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | 0 | 0 | 0 | 0 |
| Name | - | rx_sigdet_voltage_envelope_iter_done | rx_sigdet_voltage_envelope_done | rx_sigdet_voltage_envelope_error | rx_sigdet_voltage_envelope_debounce | rx_sigdet_voltage_envelope | ||||||||||||||||||||||||||
| Access | - | RO/C/V | RO/C/V | RO/C/V | RO/C/V | RO/C/V | ||||||||||||||||||||||||||
| [04:04] RO/C/V |
rx_sigdet_voltage_envelope_iter_done Reset: hex:0x0; |
| [03:03] RO/C/V |
rx_sigdet_voltage_envelope_done Reset: hex:0x0; |
| [02:02] RO/C/V |
rx_sigdet_voltage_envelope_error Reset: hex:0x0; |
| [01:01] RO/C/V |
rx_sigdet_voltage_envelope_debounce Reset: hex:0x0; |
| [00:00] RO/C/V |
rx_sigdet_voltage_envelope Reset: hex:0x0; |
+0x00000fd8 Register(32 bit) rxword_rw_spare_0
Spare RW register
Spare RW register
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782efd8 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | rxword_rw_spare_0 | |||||||||||||||||||||||||||||||
| Access | RW | |||||||||||||||||||||||||||||||
| [31:00] RW |
rxword_rw_spare_0 Reset: hex:0x00000000; |
+0x00000fdc Register(32 bit) rxword_rw_spare_1
Spare RW register
Spare RW register
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782efdc at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | rxword_rw_spare_1 | |||||||||||||||||||||||||||||||
| Access | RW | |||||||||||||||||||||||||||||||
| [31:00] RW |
rxword_rw_spare_1 Reset: hex:0x00000000; |
+0x00000fe0 Register(32 bit) rxword_rw_spare_2
Spare RW register
Spare RW register
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782efe0 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | rxword_rw_spare_2 | |||||||||||||||||||||||||||||||
| Access | RW | |||||||||||||||||||||||||||||||
| [31:00] RW |
rxword_rw_spare_2 Reset: hex:0x00000000; |
+0x00000fe4 Register(32 bit) rxword_rw_spare_3
Spare RW register
Spare RW register
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782efe4 at NOC.jesd__axi (Mem)
Access RW
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | rxword_rw_spare_3 | |||||||||||||||||||||||||||||||
| Access | RW | |||||||||||||||||||||||||||||||
| [31:00] RW |
rxword_rw_spare_3 Reset: hex:0x00000000; |
+0x00000fe8 Register(32 bit) rxword_ro_spare_0
Spare RO register
Spare RO register
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782efe8 at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | rxword_ro_spare_0 | |||||||||||||||||||||||||||||||
| Access | RO/V | |||||||||||||||||||||||||||||||
| [31:00] RO/V |
rxword_ro_spare_0 Reset: hex:0x00000000; |
+0x00000fec Register(32 bit) rxword_ro_spare_1
Spare RO register
Spare RO register
Addresses AccessRestrictions are printed as (<Agent>:<Restriction>):
0x0782efec at NOC.jesd__axi (Mem)
Access RO/V
| Reset Information | |||
|---|---|---|---|
| Prio | Type | Properties | Value/Mask (hex) |
| 0 | PowerUp | , fully affected, fully defined | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Name | rxword_ro_spare_1 | |||||||||||||||||||||||||||||||
| Access | RO/V | |||||||||||||||||||||||||||||||
| [31:00] RO/V |
rxword_ro_spare_1 Reset: hex:0x00000000; |